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-rw-r--r--src/arch/SConscript4
-rw-r--r--src/arch/alpha/isa.hh7
-rw-r--r--src/arch/alpha/registers.hh10
-rw-r--r--src/arch/alpha/utility.cc1
-rw-r--r--src/arch/arm/insts/static_inst.cc2
-rw-r--r--src/arch/arm/isa.hh7
-rw-r--r--src/arch/arm/registers.hh10
-rw-r--r--src/arch/arm/utility.cc3
-rwxr-xr-xsrc/arch/isa_parser.py115
-rw-r--r--src/arch/mips/isa.hh7
-rw-r--r--src/arch/mips/registers.hh10
-rw-r--r--src/arch/mips/utility.cc3
-rw-r--r--src/arch/null/registers.hh2
-rw-r--r--src/arch/power/insts/static_inst.cc2
-rw-r--r--src/arch/power/isa.hh7
-rw-r--r--src/arch/power/registers.hh10
-rw-r--r--src/arch/power/utility.cc3
-rw-r--r--src/arch/sparc/isa.hh7
-rw-r--r--src/arch/sparc/registers.hh9
-rw-r--r--src/arch/sparc/utility.cc3
-rw-r--r--src/arch/x86/insts/static_inst.cc7
-rw-r--r--src/arch/x86/isa.hh6
-rw-r--r--src/arch/x86/registers.hh11
-rw-r--r--src/arch/x86/utility.cc4
24 files changed, 9 insertions, 241 deletions
diff --git a/src/arch/SConscript b/src/arch/SConscript
index 89ecdfa73..e0d6845f5 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -196,7 +196,5 @@ env.Append(BUILDERS = {'ScanISA' :
DebugFlag('IntRegs')
DebugFlag('FloatRegs')
DebugFlag('CCRegs')
-DebugFlag('VectorRegs')
DebugFlag('MiscRegs')
-CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'CCRegs', 'VectorRegs',
- 'MiscRegs' ])
+CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'CCRegs', 'MiscRegs' ])
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index b5964e622..6a88ee40b 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -114,13 +114,6 @@ namespace AlphaISA
return reg;
}
- // dummy
- int
- flattenVectorIndex(int reg) const
- {
- return reg;
- }
-
int
flattenMiscIndex(int reg) const
{
diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 665ea30c7..3fd774cf7 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -56,12 +56,6 @@ typedef uint64_t MiscReg;
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;
-// vector register file entry type
-typedef uint64_t VectorRegElement;
-const int NumVectorRegElements = 0;
-const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement);
-typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg;
-
union AnyReg
{
IntReg intreg;
@@ -101,7 +95,6 @@ const int NumFloatArchRegs = 32;
const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
const int NumFloatRegs = NumFloatArchRegs;
const int NumCCRegs = 0;
-const int NumVectorRegs = 0;
const int NumMiscRegs = NUM_MISCREGS;
const int TotalNumRegs =
@@ -113,8 +106,7 @@ enum DependenceTags {
// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Reg_Base)
FP_Reg_Base = NumIntRegs,
CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
- Vector_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0
- Misc_Reg_Base = Vector_Reg_Base + NumCCRegs, // NumVectorRegs == 0
+ Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0
Max_Reg_Index = Misc_Reg_Base + NumMiscRegs + NumInternalProcRegs
};
diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index b0a503828..2dfe00f96 100644
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -73,7 +73,6 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
// Would need to add condition-code regs if implemented
assert(NumCCRegs == 0);
- assert(NumVectorRegs == 0);
// Copy misc. registers
copyMiscRegs(src, dest);
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index 417496579..9f878ac4d 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -337,8 +337,6 @@ ArmStaticInst::printReg(std::ostream &os, int reg) const
case CCRegClass:
ccprintf(os, "cc_%s", ArmISA::ccRegName[rel_reg]);
break;
- case VectorRegClass:
- panic("ARM ISA does not have any vector registers yet!");
}
}
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 1e7edd637..a07017c17 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -288,13 +288,6 @@ namespace ArmISA
}
int
- flattenVectorIndex(int reg) const
- {
- assert(reg >= 0);
- return reg;
- }
-
- int
flattenMiscIndex(int reg) const
{
assert(reg >= 0);
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index e57802e53..23fc20450 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -72,12 +72,6 @@ typedef uint64_t MiscReg;
// condition code register; must be at least 32 bits for FpCondCodes
typedef uint64_t CCReg;
-// vector register file entry type
-typedef uint64_t VectorRegElement;
-const int NumVectorRegElements = 0;
-const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement);
-typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg;
-
// Constants Related to the number of registers
const int NumIntArchRegs = NUM_ARCH_INTREGS;
// The number of single precision floating point registers
@@ -88,7 +82,6 @@ const int NumFloatSpecialRegs = 32;
const int NumIntRegs = NUM_INTREGS;
const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs;
const int NumCCRegs = NUM_CCREGS;
-const int NumVectorRegs = 0;
const int NumMiscRegs = NUM_MISCREGS;
#define ISA_HAS_CC_REGS
@@ -119,8 +112,7 @@ const int SyscallSuccessReg = ReturnValueReg;
// These help enumerate all the registers for dependence tracking.
const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1);
const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
-const int Vector_Reg_Base = CC_Reg_Base + NumCCRegs;
-const int Misc_Reg_Base = Vector_Reg_Base + NumVectorRegs;
+const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs;
const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
typedef union {
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index e1f9dfe04..34fcfd482 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -156,9 +156,6 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
for (int i = 0; i < NumCCRegs; i++)
dest->setCCReg(i, src->readCCReg(i));
- // Copy vector registers when vector registers put to use.
- assert(NumVectorRegs == 0);
-
for (int i = 0; i < NumMiscRegs; i++)
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 5050d24d4..f756161ea 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -515,9 +515,6 @@ class Operand(object):
def isCCReg(self):
return 0
- def isVectorReg(self):
- return 0
-
def isControlReg(self):
return 0
@@ -754,106 +751,6 @@ class CCRegOperand(Operand):
return wb
-class VectorRegOperand(Operand):
- def isReg(self):
- return 1
-
- def isVectorReg(self):
- return 1
-
- def __init__(self, parser, full_name, ext, is_src, is_dest):
- ## Vector registers are always treated as source registers since
- ## not the whole of them might be written, in which case we need
- ## to retain the earlier value.
- super(VectorRegOperand, self).__init__(parser, full_name, ext,
- True, is_dest)
- self.size = 0
-
- def finalize(self, predRead, predWrite):
- self.flags = self.getFlags()
- self.constructor = self.makeConstructor(predRead, predWrite)
- self.op_decl = self.makeDecl()
-
- if self.is_src:
- self.op_rd = self.makeRead(predRead)
- self.op_src_decl = self.makeDecl()
- else:
- self.op_rd = ''
- self.op_src_decl = ''
-
- if self.is_dest:
- self.op_wb = self.makeWrite(predWrite)
- self.op_dest_decl = self.makeDecl()
- else:
- self.op_wb = ''
- self.op_dest_decl = ''
-
- def makeConstructor(self, predRead, predWrite):
- c_src = ''
- c_dest = ''
-
- if self.is_src:
- c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + Vector_Reg_Base;' % \
- (self.reg_spec)
- if self.hasReadPred():
- c_src = '\n\tif (%s) {%s\n\t}' % \
- (self.read_predicate, c_src)
-
- if self.is_dest:
- c_dest = '\n\t_destRegIdx[_numDestRegs++] = %s + Vector_Reg_Base;' % \
- (self.reg_spec)
- c_dest += '\n\t_numVectorDestRegs++;'
- if self.hasWritePred():
- c_dest = '\n\tif (%s) {%s\n\t}' % \
- (self.write_predicate, c_dest)
-
- return c_src + c_dest
-
- def makeRead(self, predRead):
- if self.read_code != None:
- return self.buildReadCode('readVectorRegOperand')
-
- vector_reg_val = ''
- if predRead:
- vector_reg_val = 'xc->readVectorRegOperand(this, _sourceIndex++)'
- if self.hasReadPred():
- vector_reg_val = '(%s) ? %s : 0' % \
- (self.read_predicate, vector_reg_val)
- else:
- vector_reg_val = 'xc->readVectorRegOperand(this, %d)' % \
- self.src_reg_idx
-
- return '%s = %s;\n' % (self.base_name, vector_reg_val)
-
- def makeWrite(self, predWrite):
- if self.write_code != None:
- return self.buildWriteCode('setVectorRegOperand')
-
- if predWrite:
- wp = 'true'
- if self.hasWritePred():
- wp = self.write_predicate
-
- wcond = 'if (%s)' % (wp)
- windex = '_destIndex++'
- else:
- wcond = ''
- windex = '%d' % self.dest_reg_idx
-
- wb = '''
- %s
- {
- TheISA::VectorReg final_val = %s;
- xc->setVectorRegOperand(this, %s, final_val);\n
- if (traceData) { traceData->setData(final_val); }
- }''' % (wcond, self.base_name, windex)
-
- return wb
-
- def makeDecl(self):
- ctype = 'TheISA::VectorReg'
- return '%s %s;\n' % (ctype, self.base_name)
-
class ControlRegOperand(Operand):
def isReg(self):
return 1
@@ -921,10 +818,7 @@ class MemOperand(Operand):
# Note that initializations in the declarations are solely
# to avoid 'uninitialized variable' errors from the compiler.
# Declare memory data variable.
- if 'IsVector' in self.flags:
- return 'TheISA::VectorReg %s;\n' % self.base_name
- else:
- return '%s %s = 0;\n' % (self.ctype, self.base_name)
+ return '%s %s = 0;\n' % (self.ctype, self.base_name)
def makeRead(self, predRead):
if self.read_code != None:
@@ -1015,7 +909,6 @@ class OperandList(object):
self.numFPDestRegs = 0
self.numIntDestRegs = 0
self.numCCDestRegs = 0
- self.numVectorDestRegs = 0
self.numMiscDestRegs = 0
self.memOperand = None
@@ -1038,8 +931,6 @@ class OperandList(object):
self.numIntDestRegs += 1
elif op_desc.isCCReg():
self.numCCDestRegs += 1
- elif op_desc.isVectorReg():
- self.numVectorDestRegs += 1
elif op_desc.isControlReg():
self.numMiscDestRegs += 1
elif op_desc.isMem():
@@ -1236,7 +1127,6 @@ class InstObjParams(object):
header += '\n\t_numFPDestRegs = 0;'
header += '\n\t_numIntDestRegs = 0;'
header += '\n\t_numCCDestRegs = 0;'
- header += '\n\t_numVectorDestRegs = 0;'
self.constructor = header + \
self.operands.concatAttrStrings('constructor')
@@ -2402,8 +2292,7 @@ StaticInstPtr
operandsREString = r'''
(?<!\w) # neg. lookbehind assertion: prevent partial matches
- ((%s)(?:_(%s))?(?:\[\w+\])?) # match: operand with optional '_'
- # then suffix, and then an optional array index.
+ ((%s)(?:_(%s))?) # match: operand with optional '_' then suffix
(?!\w) # neg. lookahead assertion: prevent partial matches
''' % (string.join(operands, '|'), string.join(extensions, '|'))
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index f61db6d57..feb55e473 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -184,13 +184,6 @@ namespace MipsISA
return reg;
}
- // dummy
- int
- flattenVectorIndex(int reg) const
- {
- return reg;
- }
-
int
flattenMiscIndex(int reg) const
{
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index e7d5e346c..0ac84cc7f 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -55,7 +55,6 @@ const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
const int NumCCRegs = 0;
-const int NumVectorRegs = 0;
const uint32_t MIPS32_QNAN = 0x7fbfffff;
const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff);
@@ -279,8 +278,7 @@ const int NumMiscRegs = MISCREG_NUMREGS;
// These help enumerate all the registers for dependence tracking.
const int FP_Reg_Base = NumIntRegs;
const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
-const int Vector_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
-const int Misc_Reg_Base = Vector_Reg_Base + NumVectorRegs;
+const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
@@ -299,12 +297,6 @@ typedef uint64_t MiscReg;
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;
-// vector register file entry type
-typedef uint64_t VectorRegElement;
-const int NumVectorRegElements = 0;
-const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement);
-typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg;
-
typedef union {
IntReg intreg;
FloatReg fpreg;
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 92ca8c6f0..80047fbfd 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -252,9 +252,6 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
// Would need to add condition-code regs if implemented
assert(NumCCRegs == 0);
- // Copy vector registers when vector registers put to use.
- assert(NumVectorRegs == 0);
-
// Copy misc. registers
for (int i = 0; i < NumMiscRegs; i++)
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index 3f1524554..1e52fc5a6 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -49,8 +49,6 @@ typedef uint32_t FloatRegBits;
typedef float FloatReg;
typedef uint8_t CCReg;
typedef uint64_t MiscReg;
-typedef uint64_t VectorRegElement;
-typedef std::array<VectorRegElement, 0> VectorReg;
}
diff --git a/src/arch/power/insts/static_inst.cc b/src/arch/power/insts/static_inst.cc
index 5bd16b40d..087e1f740 100644
--- a/src/arch/power/insts/static_inst.cc
+++ b/src/arch/power/insts/static_inst.cc
@@ -57,8 +57,6 @@ PowerStaticInst::printReg(std::ostream &os, int reg) const
}
case CCRegClass:
panic("printReg: POWER does not implement CCRegClass\n");
- case VectorRegClass:
- panic("printReg: POWER does not implement VectorRegClass\n");
}
}
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 08ee82d5d..aaf5bd92a 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -105,13 +105,6 @@ class ISA : public SimObject
return reg;
}
- // dummy
- int
- flattenVectorIndex(int reg) const
- {
- return reg;
- }
-
int
flattenMiscIndex(int reg) const
{
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 1d0b4a21f..abee516fc 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -55,12 +55,6 @@ typedef uint64_t MiscReg;
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;
-// typedefs for Vector registers
-const int NumVectorRegElements = 0;
-typedef uint64_t VectorRegElement;
-const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement);
-typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg;
-
// Constants Related to the number of registers
const int NumIntArchRegs = 32;
@@ -74,7 +68,6 @@ const int NumInternalProcRegs = 0;
const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
const int NumCCRegs = 0;
-const int NumVectorRegs = 0;
const int NumMiscRegs = NUM_MISCREGS;
// Semantically meaningful register indices
@@ -97,8 +90,7 @@ const int SyscallSuccessReg = 3;
// These help enumerate all the registers for dependence tracking.
const int FP_Reg_Base = NumIntRegs;
const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
-const int Vector_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
-const int Misc_Reg_Base = Vector_Reg_Base + NumVectorRegs; // NumVectorRegs == 0
+const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
typedef union {
diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc
index fa2a1d89b..7be195b8d 100644
--- a/src/arch/power/utility.cc
+++ b/src/arch/power/utility.cc
@@ -51,9 +51,6 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
// Would need to add condition-code regs if implemented
assert(NumCCRegs == 0);
- // Copy vector registers when vector registers put to use.
- assert(NumVectorRegs == 0);
-
// Copy misc. registers
copyMiscRegs(src, dest);
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 51e797c90..1d2a457d2 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -211,13 +211,6 @@ class ISA : public SimObject
return reg;
}
- // dummy
- int
- flattenVectorIndex(int reg) const
- {
- return reg;
- }
-
int
flattenMiscIndex(int reg) const
{
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index a59139ba2..b25f34584 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -51,11 +51,6 @@ typedef uint32_t FloatRegBits;
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;
-// vector register file entry type
-typedef uint64_t VectorRegElement;
-const int NumVectorRegElements = 0;
-const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement);
-typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg;
typedef union
{
@@ -80,7 +75,6 @@ const int SyscallPseudoReturnReg = 9;
const int NumIntArchRegs = 32;
const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
const int NumCCRegs = 0;
-const int NumVectorRegs = 0;
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
@@ -88,8 +82,7 @@ const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
enum DependenceTags {
FP_Reg_Base = NumIntRegs,
CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
- Vector_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0
- Misc_Reg_Base = Vector_Reg_Base + NumVectorRegs, // NumVectorRegs == 0
+ Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0
Max_Reg_Index = Misc_Reg_Base + NumMiscRegs,
};
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index 6d7a1ba95..34d4f79b3 100644
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -237,9 +237,6 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
// Would need to add condition-code regs if implemented
assert(NumCCRegs == 0);
- // Copy vector registers when vector registers put to use.
- assert(NumVectorRegs == 0);
-
// Copy misc. registers
copyMiscRegs(src, dest);
diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc
index 49ea6ef4e..39091289f 100644
--- a/src/arch/x86/insts/static_inst.cc
+++ b/src/arch/x86/insts/static_inst.cc
@@ -225,19 +225,12 @@ namespace X86ISA
ccprintf(os, "%%cc%d", rel_reg);
break;
- case VectorRegClass:
- ccprintf(os, "%%cc%d", rel_reg);
- break;
-
case MiscRegClass:
switch (rel_reg) {
default:
ccprintf(os, "%%ctrl%d", rel_reg);
}
break;
-
- default:
- panic("Invalid register class!\n");
}
}
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 779241c55..88f4980ae 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -92,12 +92,6 @@ namespace X86ISA
}
int
- flattenVectorIndex(int reg) const
- {
- return reg;
- }
-
- int
flattenMiscIndex(int reg) const
{
return reg;
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index ad40fe17f..ebd88136e 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -57,7 +57,6 @@ const int NumMiscRegs = NUM_MISCREGS;
const int NumIntArchRegs = NUM_INTREGS;
const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs;
const int NumCCRegs = NUM_CCREGS;
-const int NumVectorRegs = 0;
#define ISA_HAS_CC_REGS
@@ -73,8 +72,7 @@ enum DependenceTags {
// we just start at (1 << 7) == 128.
FP_Reg_Base = 128,
CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
- Vector_Reg_Base = CC_Reg_Base + NumCCRegs,
- Misc_Reg_Base = Vector_Reg_Base + NumVectorRegs,
+ Misc_Reg_Base = CC_Reg_Base + NumCCRegs,
Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
};
@@ -93,13 +91,6 @@ const int SyscallPseudoReturnReg = INTREG_RDX;
typedef uint64_t IntReg;
typedef uint64_t CCReg;
-
-// vector register file entry type
-typedef uint64_t VectorRegElement;
-const int NumVectorRegElements = 0;
-const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement);
-typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg;
-
//XXX Should this be a 128 bit structure for XMM memory ops?
typedef uint64_t LargestRead;
typedef uint64_t MiscReg;
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index e1be61180..f7d0f816e 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -245,10 +245,6 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
//copy condition-code regs
for (int i = 0; i < NumCCRegs; ++i)
dest->setCCRegFlat(i, src->readCCRegFlat(i));
-
- // copy vector regs when added to the architecture
- assert(NumVectorRegs == 0);
-
copyMiscRegs(src, dest);
dest->pcState(src->pcState());
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 03:13:32 +0000