summaryrefslogtreecommitdiff
path: root/src/arch
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/alpha/miscregfile.cc20
-rw-r--r--src/arch/alpha/tlb.cc924
-rwxr-xr-xsrc/arch/isa_parser.py25
-rw-r--r--src/arch/mips/isa/formats/fp.isa6
-rw-r--r--src/arch/mips/mmaped_ipr.hh3
-rw-r--r--src/arch/sparc/miscregfile.cc18
-rw-r--r--src/arch/sparc/tlb.cc127
-rw-r--r--src/arch/sparc/tlb.hh11
8 files changed, 617 insertions, 517 deletions
diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc
index 962d4609f..67f6c98e4 100644
--- a/src/arch/alpha/miscregfile.cc
+++ b/src/arch/alpha/miscregfile.cc
@@ -89,12 +89,26 @@ namespace AlphaISA
MiscReg
MiscRegFile::readRegWithEffect(int misc_reg, ThreadContext *tc)
{
+ switch(misc_reg) {
+ case MISCREG_FPCR:
+ return fpcr;
+ case MISCREG_UNIQ:
+ return uniq;
+ case MISCREG_LOCKFLAG:
+ return lock_flag;
+ case MISCREG_LOCKADDR:
+ return lock_addr;
+ case MISCREG_INTR:
+ return intr_flag;
#if FULL_SYSTEM
- return readIpr(misc_reg, tc);
+ default:
+ return readIpr(misc_reg, tc);
#else
- panic("No faulting misc regs in SE mode!");
- return 0;
+ default:
+ panic("No faulting misc regs in SE mode!");
+ return 0;
#endif
+ }
}
void
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index af69e45c0..c21bf94f5 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -48,589 +48,589 @@ using namespace EV5;
namespace AlphaISA
{
- ///////////////////////////////////////////////////////////////////////
- //
- // Alpha TLB
- //
+///////////////////////////////////////////////////////////////////////
+//
+// Alpha TLB
+//
#ifdef DEBUG
- bool uncacheBit39 = false;
- bool uncacheBit40 = false;
+bool uncacheBit39 = false;
+bool uncacheBit40 = false;
#endif
#define MODE2MASK(X) (1 << (X))
- TLB::TLB(const string &name, int s)
- : SimObject(name), size(s), nlu(0)
- {
- table = new PTE[size];
- memset(table, 0, sizeof(PTE[size]));
- }
+TLB::TLB(const string &name, int s)
+ : SimObject(name), size(s), nlu(0)
+{
+ table = new PTE[size];
+ memset(table, 0, sizeof(PTE[size]));
+}
- TLB::~TLB()
- {
- if (table)
- delete [] table;
- }
+TLB::~TLB()
+{
+ if (table)
+ delete [] table;
+}
- // look up an entry in the TLB
- PTE *
- TLB::lookup(Addr vpn, uint8_t asn) const
- {
- // assume not found...
- PTE *retval = NULL;
-
- PageTable::const_iterator i = lookupTable.find(vpn);
- if (i != lookupTable.end()) {
- while (i->first == vpn) {
- int index = i->second;
- PTE *pte = &table[index];
- assert(pte->valid);
- if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
- retval = pte;
- break;
- }
+// look up an entry in the TLB
+PTE *
+TLB::lookup(Addr vpn, uint8_t asn) const
+{
+ // assume not found...
+ PTE *retval = NULL;
- ++i;
+ PageTable::const_iterator i = lookupTable.find(vpn);
+ if (i != lookupTable.end()) {
+ while (i->first == vpn) {
+ int index = i->second;
+ PTE *pte = &table[index];
+ assert(pte->valid);
+ if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
+ retval = pte;
+ break;
}
- }
- DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
- retval ? "hit" : "miss", retval ? retval->ppn : 0);
- return retval;
+ ++i;
+ }
}
+ DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
+ retval ? "hit" : "miss", retval ? retval->ppn : 0);
+ return retval;
+}
- Fault
- TLB::checkCacheability(RequestPtr &req)
- {
- // in Alpha, cacheability is controlled by upper-level bits of the
- // physical address
- /*
- * We support having the uncacheable bit in either bit 39 or bit 40.
- * The Turbolaser platform (and EV5) support having the bit in 39, but
- * Tsunami (which Linux assumes uses an EV6) generates accesses with
- * the bit in 40. So we must check for both, but we have debug flags
- * to catch a weird case where both are used, which shouldn't happen.
- */
+Fault
+TLB::checkCacheability(RequestPtr &req)
+{
+// in Alpha, cacheability is controlled by upper-level bits of the
+// physical address
+
+/*
+ * We support having the uncacheable bit in either bit 39 or bit 40.
+ * The Turbolaser platform (and EV5) support having the bit in 39, but
+ * Tsunami (which Linux assumes uses an EV6) generates accesses with
+ * the bit in 40. So we must check for both, but we have debug flags
+ * to catch a weird case where both are used, which shouldn't happen.
+ */
#if ALPHA_TLASER
- if (req->getPaddr() & PAddrUncachedBit39) {
+ if (req->getPaddr() & PAddrUncachedBit39) {
#else
- if (req->getPaddr() & PAddrUncachedBit43) {
+ if (req->getPaddr() & PAddrUncachedBit43) {
#endif
- // IPR memory space not implemented
- if (PAddrIprSpace(req->getPaddr())) {
- return new UnimpFault("IPR memory space not implemented!");
- } else {
- // mark request as uncacheable
- req->setFlags(req->getFlags() | UNCACHEABLE);
+ // IPR memory space not implemented
+ if (PAddrIprSpace(req->getPaddr())) {
+ return new UnimpFault("IPR memory space not implemented!");
+ } else {
+ // mark request as uncacheable
+ req->setFlags(req->getFlags() | UNCACHEABLE);
#if !ALPHA_TLASER
- // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
- req->setPaddr(req->getPaddr() & PAddrUncachedMask);
+ // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
+ req->setPaddr(req->getPaddr() & PAddrUncachedMask);
#endif
- }
}
- return NoFault;
}
+ return NoFault;
+}
- // insert a new TLB entry
- void
- TLB::insert(Addr addr, PTE &pte)
- {
- VAddr vaddr = addr;
- if (table[nlu].valid) {
- Addr oldvpn = table[nlu].tag;
- PageTable::iterator i = lookupTable.find(oldvpn);
-
- if (i == lookupTable.end())
- panic("TLB entry not found in lookupTable");
-
- int index;
- while ((index = i->second) != nlu) {
- if (table[index].tag != oldvpn)
- panic("TLB entry not found in lookupTable");
+// insert a new TLB entry
+void
+TLB::insert(Addr addr, PTE &pte)
+{
+ VAddr vaddr = addr;
+ if (table[nlu].valid) {
+ Addr oldvpn = table[nlu].tag;
+ PageTable::iterator i = lookupTable.find(oldvpn);
- ++i;
- }
+ if (i == lookupTable.end())
+ panic("TLB entry not found in lookupTable");
- DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
+ int index;
+ while ((index = i->second) != nlu) {
+ if (table[index].tag != oldvpn)
+ panic("TLB entry not found in lookupTable");
- lookupTable.erase(i);
+ ++i;
}
- DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn);
+ DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
- table[nlu] = pte;
- table[nlu].tag = vaddr.vpn();
- table[nlu].valid = true;
-
- lookupTable.insert(make_pair(vaddr.vpn(), nlu));
- nextnlu();
+ lookupTable.erase(i);
}
- void
- TLB::flushAll()
- {
- DPRINTF(TLB, "flushAll\n");
- memset(table, 0, sizeof(PTE[size]));
- lookupTable.clear();
- nlu = 0;
- }
+ DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn);
- void
- TLB::flushProcesses()
- {
- PageTable::iterator i = lookupTable.begin();
- PageTable::iterator end = lookupTable.end();
- while (i != end) {
- int index = i->second;
- PTE *pte = &table[index];
- assert(pte->valid);
+ table[nlu] = pte;
+ table[nlu].tag = vaddr.vpn();
+ table[nlu].valid = true;
- // we can't increment i after we erase it, so save a copy and
- // increment it to get the next entry now
- PageTable::iterator cur = i;
- ++i;
+ lookupTable.insert(make_pair(vaddr.vpn(), nlu));
+ nextnlu();
+}
- if (!pte->asma) {
- DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn);
- pte->valid = false;
- lookupTable.erase(cur);
- }
+void
+TLB::flushAll()
+{
+ DPRINTF(TLB, "flushAll\n");
+ memset(table, 0, sizeof(PTE[size]));
+ lookupTable.clear();
+ nlu = 0;
+}
+
+void
+TLB::flushProcesses()
+{
+ PageTable::iterator i = lookupTable.begin();
+ PageTable::iterator end = lookupTable.end();
+ while (i != end) {
+ int index = i->second;
+ PTE *pte = &table[index];
+ assert(pte->valid);
+
+ // we can't increment i after we erase it, so save a copy and
+ // increment it to get the next entry now
+ PageTable::iterator cur = i;
+ ++i;
+
+ if (!pte->asma) {
+ DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn);
+ pte->valid = false;
+ lookupTable.erase(cur);
}
}
+}
- void
- TLB::flushAddr(Addr addr, uint8_t asn)
- {
- VAddr vaddr = addr;
+void
+TLB::flushAddr(Addr addr, uint8_t asn)
+{
+ VAddr vaddr = addr;
- PageTable::iterator i = lookupTable.find(vaddr.vpn());
- if (i == lookupTable.end())
- return;
+ PageTable::iterator i = lookupTable.find(vaddr.vpn());
+ if (i == lookupTable.end())
+ return;
- while (i->first == vaddr.vpn()) {
- int index = i->second;
- PTE *pte = &table[index];
- assert(pte->valid);
-
- if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) {
- DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
- pte->ppn);
+ while (i->first == vaddr.vpn()) {
+ int index = i->second;
+ PTE *pte = &table[index];
+ assert(pte->valid);
- // invalidate this entry
- pte->valid = false;
+ if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) {
+ DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
+ pte->ppn);
- lookupTable.erase(i);
- }
+ // invalidate this entry
+ pte->valid = false;
- ++i;
+ lookupTable.erase(i);
}
+
+ ++i;
}
+}
- void
- TLB::serialize(ostream &os)
- {
- SERIALIZE_SCALAR(size);
- SERIALIZE_SCALAR(nlu);
+void
+TLB::serialize(ostream &os)
+{
+ SERIALIZE_SCALAR(size);
+ SERIALIZE_SCALAR(nlu);
- for (int i = 0; i < size; i++) {
- nameOut(os, csprintf("%s.PTE%d", name(), i));
- table[i].serialize(os);
- }
+ for (int i = 0; i < size; i++) {
+ nameOut(os, csprintf("%s.PTE%d", name(), i));
+ table[i].serialize(os);
}
+}
- void
- TLB::unserialize(Checkpoint *cp, const string &section)
- {
- UNSERIALIZE_SCALAR(size);
- UNSERIALIZE_SCALAR(nlu);
+void
+TLB::unserialize(Checkpoint *cp, const string &section)
+{
+ UNSERIALIZE_SCALAR(size);
+ UNSERIALIZE_SCALAR(nlu);
- for (int i = 0; i < size; i++) {
- table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
- if (table[i].valid) {
- lookupTable.insert(make_pair(table[i].tag, i));
- }
+ for (int i = 0; i < size; i++) {
+ table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
+ if (table[i].valid) {
+ lookupTable.insert(make_pair(table[i].tag, i));
}
}
+}
- ///////////////////////////////////////////////////////////////////////
- //
- // Alpha ITB
- //
- ITB::ITB(const std::string &name, int size)
- : TLB(name, size)
- {}
-
-
- void
- ITB::regStats()
- {
- hits
- .name(name() + ".hits")
- .desc("ITB hits");
- misses
- .name(name() + ".misses")
- .desc("ITB misses");
- acv
- .name(name() + ".acv")
- .desc("ITB acv");
- accesses
- .name(name() + ".accesses")
- .desc("ITB accesses");
-
- accesses = hits + misses;
- }
+///////////////////////////////////////////////////////////////////////
+//
+// Alpha ITB
+//
+ITB::ITB(const std::string &name, int size)
+ : TLB(name, size)
+{}
- Fault
- ITB::translate(RequestPtr &req, ThreadContext *tc) const
- {
- if (PcPAL(req->getPC())) {
- // strip off PAL PC marker (lsb is 1)
- req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
- hits++;
- return NoFault;
- }
+void
+ITB::regStats()
+{
+ hits
+ .name(name() + ".hits")
+ .desc("ITB hits");
+ misses
+ .name(name() + ".misses")
+ .desc("ITB misses");
+ acv
+ .name(name() + ".acv")
+ .desc("ITB acv");
+ accesses
+ .name(name() + ".accesses")
+ .desc("ITB accesses");
+
+ accesses = hits + misses;
+}
- if (req->getFlags() & PHYSICAL) {
- req->setPaddr(req->getVaddr());
- } else {
- // verify that this is a good virtual address
- if (!validVirtualAddress(req->getVaddr())) {
- acv++;
- return new ItbAcvFault(req->getVaddr());
- }
+Fault
+ITB::translate(RequestPtr &req, ThreadContext *tc) const
+{
+ if (PcPAL(req->getPC())) {
+ // strip off PAL PC marker (lsb is 1)
+ req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
+ hits++;
+ return NoFault;
+ }
+
+ if (req->getFlags() & PHYSICAL) {
+ req->setPaddr(req->getVaddr());
+ } else {
+ // verify that this is a good virtual address
+ if (!validVirtualAddress(req->getVaddr())) {
+ acv++;
+ return new ItbAcvFault(req->getVaddr());
+ }
- // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
- // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
+
+ // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
+ // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
#if ALPHA_TLASER
- if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) &&
- VAddrSpaceEV5(req->getVaddr()) == 2) {
+ if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) &&
+ VAddrSpaceEV5(req->getVaddr()) == 2) {
#else
- if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
+ if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
#endif
- // only valid in kernel mode
- if (ICM_CM(tc->readMiscReg(IPR_ICM)) !=
- mode_kernel) {
- acv++;
- return new ItbAcvFault(req->getVaddr());
- }
+ // only valid in kernel mode
+ if (ICM_CM(tc->readMiscReg(IPR_ICM)) !=
+ mode_kernel) {
+ acv++;
+ return new ItbAcvFault(req->getVaddr());
+ }
- req->setPaddr(req->getVaddr() & PAddrImplMask);
+ req->setPaddr(req->getVaddr() & PAddrImplMask);
#if !ALPHA_TLASER
- // sign extend the physical address properly
- if (req->getPaddr() & PAddrUncachedBit40)
- req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
- else
- req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
+ // sign extend the physical address properly
+ if (req->getPaddr() & PAddrUncachedBit40)
+ req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
+ else
+ req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
#endif
- } else {
- // not a physical address: need to look up pte
- int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN));
- PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
- asn);
-
- if (!pte) {
- misses++;
- return new ItbPageFault(req->getVaddr());
- }
-
- req->setPaddr((pte->ppn << PageShift) +
- (VAddr(req->getVaddr()).offset()
- & ~3));
+ } else {
+ // not a physical address: need to look up pte
+ int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN));
+ PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
+ asn);
+
+ if (!pte) {
+ misses++;
+ return new ItbPageFault(req->getVaddr());
+ }
- // check permissions for this access
- if (!(pte->xre &
- (1 << ICM_CM(tc->readMiscReg(IPR_ICM))))) {
- // instruction access fault
- acv++;
- return new ItbAcvFault(req->getVaddr());
- }
+ req->setPaddr((pte->ppn << PageShift) +
+ (VAddr(req->getVaddr()).offset()
+ & ~3));
- hits++;
+ // check permissions for this access
+ if (!(pte->xre &
+ (1 << ICM_CM(tc->readMiscReg(IPR_ICM))))) {
+ // instruction access fault
+ acv++;
+ return new ItbAcvFault(req->getVaddr());
}
+
+ hits++;
}
+ }
- // check that the physical address is ok (catch bad physical addresses)
- if (req->getPaddr() & ~PAddrImplMask)
- return genMachineCheckFault();
+ // check that the physical address is ok (catch bad physical addresses)
+ if (req->getPaddr() & ~PAddrImplMask)
+ return genMachineCheckFault();
- return checkCacheability(req);
+ return checkCacheability(req);
- }
+}
- ///////////////////////////////////////////////////////////////////////
- //
- // Alpha DTB
- //
- DTB::DTB(const std::string &name, int size)
- : TLB(name, size)
- {}
-
- void
- DTB::regStats()
- {
- read_hits
- .name(name() + ".read_hits")
- .desc("DTB read hits")
- ;
-
- read_misses
- .name(name() + ".read_misses")
- .desc("DTB read misses")
- ;
-
- read_acv
- .name(name() + ".read_acv")
- .desc("DTB read access violations")
- ;
-
- read_accesses
- .name(name() + ".read_accesses")
- .desc("DTB read accesses")
- ;
-
- write_hits
- .name(name() + ".write_hits")
- .desc("DTB write hits")
- ;
-
- write_misses
- .name(name() + ".write_misses")
- .desc("DTB write misses")
- ;
-
- write_acv
- .name(name() + ".write_acv")
- .desc("DTB write access violations")
- ;
-
- write_accesses
- .name(name() + ".write_accesses")
- .desc("DTB write accesses")
- ;
-
- hits
- .name(name() + ".hits")
- .desc("DTB hits")
- ;
-
- misses
- .name(name() + ".misses")
- .desc("DTB misses")
- ;
-
- acv
- .name(name() + ".acv")
- .desc("DTB access violations")
- ;
-
- accesses
- .name(name() + ".accesses")
- .desc("DTB accesses")
- ;
-
- hits = read_hits + write_hits;
- misses = read_misses + write_misses;
- acv = read_acv + write_acv;
- accesses = read_accesses + write_accesses;
- }
+///////////////////////////////////////////////////////////////////////
+//
+// Alpha DTB
+//
+ DTB::DTB(const std::string &name, int size)
+ : TLB(name, size)
+{}
- Fault
- DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
- {
- Addr pc = tc->readPC();
+void
+DTB::regStats()
+{
+ read_hits
+ .name(name() + ".read_hits")
+ .desc("DTB read hits")
+ ;
+
+ read_misses
+ .name(name() + ".read_misses")
+ .desc("DTB read misses")
+ ;
+
+ read_acv
+ .name(name() + ".read_acv")
+ .desc("DTB read access violations")
+ ;
+
+ read_accesses
+ .name(name() + ".read_accesses")
+ .desc("DTB read accesses")
+ ;
+
+ write_hits
+ .name(name() + ".write_hits")
+ .desc("DTB write hits")
+ ;
+
+ write_misses
+ .name(name() + ".write_misses")
+ .desc("DTB write misses")
+ ;
+
+ write_acv
+ .name(name() + ".write_acv")
+ .desc("DTB write access violations")
+ ;
+
+ write_accesses
+ .name(name() + ".write_accesses")
+ .desc("DTB write accesses")
+ ;
+
+ hits
+ .name(name() + ".hits")
+ .desc("DTB hits")
+ ;
+
+ misses
+ .name(name() + ".misses")
+ .desc("DTB misses")
+ ;
+
+ acv
+ .name(name() + ".acv")
+ .desc("DTB access violations")
+ ;
+
+ accesses
+ .name(name() + ".accesses")
+ .desc("DTB accesses")
+ ;
+
+ hits = read_hits + write_hits;
+ misses = read_misses + write_misses;
+ acv = read_acv + write_acv;
+ accesses = read_accesses + write_accesses;
+}
- mode_type mode =
- (mode_type)DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM));
+Fault
+DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
+{
+ Addr pc = tc->readPC();
+ mode_type mode =
+ (mode_type)DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM));
- /**
- * Check for alignment faults
- */
- if (req->getVaddr() & (req->getSize() - 1)) {
- DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
- req->getSize());
- uint64_t flags = write ? MM_STAT_WR_MASK : 0;
- return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
- }
- if (pc & 0x1) {
- mode = (req->getFlags() & ALTMODE) ?
- (mode_type)ALT_MODE_AM(
- tc->readMiscReg(IPR_ALT_MODE))
- : mode_kernel;
- }
+ /**
+ * Check for alignment faults
+ */
+ if (req->getVaddr() & (req->getSize() - 1)) {
+ DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
+ req->getSize());
+ uint64_t flags = write ? MM_STAT_WR_MASK : 0;
+ return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
+ }
- if (req->getFlags() & PHYSICAL) {
- req->setPaddr(req->getVaddr());
- } else {
- // verify that this is a good virtual address
- if (!validVirtualAddress(req->getVaddr())) {
- if (write) { write_acv++; } else { read_acv++; }
- uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
- MM_STAT_BAD_VA_MASK |
- MM_STAT_ACV_MASK;
- return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
- }
+ if (PcPAL(pc)) {
+ mode = (req->getFlags() & ALTMODE) ?
+ (mode_type)ALT_MODE_AM(
+ tc->readMiscReg(IPR_ALT_MODE))
+ : mode_kernel;
+ }
- // Check for "superpage" mapping
+ if (req->getFlags() & PHYSICAL) {
+ req->setPaddr(req->getVaddr());
+ } else {
+ // verify that this is a good virtual address
+ if (!validVirtualAddress(req->getVaddr())) {
+ if (write) { write_acv++; } else { read_acv++; }
+ uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
+ MM_STAT_BAD_VA_MASK |
+ MM_STAT_ACV_MASK;
+ return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
+ }
+
+ // Check for "superpage" mapping
#if ALPHA_TLASER
- if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) &&
- VAddrSpaceEV5(req->getVaddr()) == 2) {
+ if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) &&
+ VAddrSpaceEV5(req->getVaddr()) == 2) {
#else
- if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
+ if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
#endif
- // only valid in kernel mode
- if (DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)) !=
- mode_kernel) {
- if (write) { write_acv++; } else { read_acv++; }
- uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
- MM_STAT_ACV_MASK);
- return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
- }
+ // only valid in kernel mode
+ if (DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)) !=
+ mode_kernel) {
+ if (write) { write_acv++; } else { read_acv++; }
+ uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
+ MM_STAT_ACV_MASK);
+ return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
+ }
- req->setPaddr(req->getVaddr() & PAddrImplMask);
+ req->setPaddr(req->getVaddr() & PAddrImplMask);
#if !ALPHA_TLASER
- // sign extend the physical address properly
- if (req->getPaddr() & PAddrUncachedBit40)
- req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
- else
- req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
+ // sign extend the physical address properly
+ if (req->getPaddr() & PAddrUncachedBit40)
+ req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
+ else
+ req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
#endif
+ } else {
+ if (write)
+ write_accesses++;
+ else
+ read_accesses++;
+
+ int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN));
+
+ // not a physical address: need to look up pte
+ PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
+ asn);
+
+ if (!pte) {
+ // page fault
+ if (write) { write_misses++; } else { read_misses++; }
+ uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
+ MM_STAT_DTB_MISS_MASK;
+ return (req->getFlags() & VPTE) ?
+ (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
+ flags)) :
+ (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
+ flags));
+ }
+
+ req->setPaddr((pte->ppn << PageShift) +
+ VAddr(req->getVaddr()).offset());
+
+ if (write) {
+ if (!(pte->xwe & MODE2MASK(mode))) {
+ // declare the instruction access fault
+ write_acv++;
+ uint64_t flags = MM_STAT_WR_MASK |
+ MM_STAT_ACV_MASK |
+ (pte->fonw ? MM_STAT_FONW_MASK : 0);
+ return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
+ }
+ if (pte->fonw) {
+ write_acv++;
+ uint64_t flags = MM_STAT_WR_MASK |
+ MM_STAT_FONW_MASK;
+ return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
+ }
} else {
- if (write)
- write_accesses++;
- else
- read_accesses++;
-
- int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN));
-
- // not a physical address: need to look up pte
- PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
- asn);
-
- if (!pte) {
- // page fault
- if (write) { write_misses++; } else { read_misses++; }
- uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
- MM_STAT_DTB_MISS_MASK;
- return (req->getFlags() & VPTE) ?
- (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
- flags)) :
- (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
- flags));
+ if (!(pte->xre & MODE2MASK(mode))) {
+ read_acv++;
+ uint64_t flags = MM_STAT_ACV_MASK |
+ (pte->fonr ? MM_STAT_FONR_MASK : 0);
+ return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
}
-
- req->setPaddr((pte->ppn << PageShift) +
- VAddr(req->getVaddr()).offset());
-
- if (write) {
- if (!(pte->xwe & MODE2MASK(mode))) {
- // declare the instruction access fault
- write_acv++;
- uint64_t flags = MM_STAT_WR_MASK |
- MM_STAT_ACV_MASK |
- (pte->fonw ? MM_STAT_FONW_MASK : 0);
- return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
- }
- if (pte->fonw) {
- write_acv++;
- uint64_t flags = MM_STAT_WR_MASK |
- MM_STAT_FONW_MASK;
- return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
- }
- } else {
- if (!(pte->xre & MODE2MASK(mode))) {
- read_acv++;
- uint64_t flags = MM_STAT_ACV_MASK |
- (pte->fonr ? MM_STAT_FONR_MASK : 0);
- return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
- }
- if (pte->fonr) {
- read_acv++;
- uint64_t flags = MM_STAT_FONR_MASK;
- return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
- }
+ if (pte->fonr) {
+ read_acv++;
+ uint64_t flags = MM_STAT_FONR_MASK;
+ return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
}
}
-
- if (write)
- write_hits++;
- else
- read_hits++;
}
- // check that the physical address is ok (catch bad physical addresses)
- if (req->getPaddr() & ~PAddrImplMask)
- return genMachineCheckFault();
-
- return checkCacheability(req);
+ if (write)
+ write_hits++;
+ else
+ read_hits++;
}
- PTE &
- TLB::index(bool advance)
- {
- PTE *pte = &table[nlu];
+ // check that the physical address is ok (catch bad physical addresses)
+ if (req->getPaddr() & ~PAddrImplMask)
+ return genMachineCheckFault();
- if (advance)
- nextnlu();
+ return checkCacheability(req);
+}
- return *pte;
- }
+PTE &
+TLB::index(bool advance)
+{
+ PTE *pte = &table[nlu];
+
+ if (advance)
+ nextnlu();
- DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB)
+ return *pte;
+}
- BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
+DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB)
- Param<int> size;
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
- END_DECLARE_SIM_OBJECT_PARAMS(ITB)
+ Param<int> size;
- BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
+END_DECLARE_SIM_OBJECT_PARAMS(ITB)
- INIT_PARAM_DFLT(size, "TLB size", 48)
+BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
- END_INIT_SIM_OBJECT_PARAMS(ITB)
+ INIT_PARAM_DFLT(size, "TLB size", 48)
+END_INIT_SIM_OBJECT_PARAMS(ITB)
- CREATE_SIM_OBJECT(ITB)
- {
- return new ITB(getInstanceName(), size);
- }
- REGISTER_SIM_OBJECT("AlphaITB", ITB)
+CREATE_SIM_OBJECT(ITB)
+{
+ return new ITB(getInstanceName(), size);
+}
- BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
+REGISTER_SIM_OBJECT("AlphaITB", ITB)
- Param<int> size;
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
- END_DECLARE_SIM_OBJECT_PARAMS(DTB)
+ Param<int> size;
- BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
+END_DECLARE_SIM_OBJECT_PARAMS(DTB)
- INIT_PARAM_DFLT(size, "TLB size", 64)
+BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
- END_INIT_SIM_OBJECT_PARAMS(DTB)
+ INIT_PARAM_DFLT(size, "TLB size", 64)
+END_INIT_SIM_OBJECT_PARAMS(DTB)
- CREATE_SIM_OBJECT(DTB)
- {
- return new DTB(getInstanceName(), size);
- }
- REGISTER_SIM_OBJECT("AlphaDTB", DTB)
+CREATE_SIM_OBJECT(DTB)
+{
+ return new DTB(getInstanceName(), size);
+}
+
+REGISTER_SIM_OBJECT("AlphaDTB", DTB)
}
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 2086473d6..59eb18c9c 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1180,15 +1180,16 @@ class IntRegOperand(Operand):
if (self.ctype == 'float' or self.ctype == 'double'):
error(0, 'Attempt to read integer register as FP')
if (self.size == self.dflt_size):
- return '%s = xc->readIntReg(this, %d);\n' % \
+ return '%s = xc->readIntRegOperand(this, %d);\n' % \
(self.base_name, self.src_reg_idx)
elif (self.size > self.dflt_size):
- int_reg_val = 'xc->readIntReg(this, %d)' % (self.src_reg_idx)
+ int_reg_val = 'xc->readIntRegOperand(this, %d)' % \
+ (self.src_reg_idx)
if (self.is_signed):
int_reg_val = 'sext<%d>(%s)' % (self.dflt_size, int_reg_val)
return '%s = %s;\n' % (self.base_name, int_reg_val)
else:
- return '%s = bits(xc->readIntReg(this, %d), %d, 0);\n' % \
+ return '%s = bits(xc->readIntRegOperand(this, %d), %d, 0);\n' % \
(self.base_name, self.src_reg_idx, self.size-1)
def makeWrite(self):
@@ -1201,7 +1202,7 @@ class IntRegOperand(Operand):
wb = '''
{
%s final_val = %s;
- xc->setIntReg(this, %d, final_val);\n
+ xc->setIntRegOperand(this, %d, final_val);\n
if (traceData) { traceData->setData(final_val); }
}''' % (self.dflt_ctype, final_val, self.dest_reg_idx)
return wb
@@ -1227,13 +1228,13 @@ class FloatRegOperand(Operand):
bit_select = 0
width = 0;
if (self.ctype == 'float'):
- func = 'readFloatReg'
+ func = 'readFloatRegOperand'
width = 32;
elif (self.ctype == 'double'):
- func = 'readFloatReg'
+ func = 'readFloatRegOperand'
width = 64;
else:
- func = 'readFloatRegBits'
+ func = 'readFloatRegOperandBits'
if (self.ctype == 'uint32_t'):
width = 32;
elif (self.ctype == 'uint64_t'):
@@ -1259,18 +1260,18 @@ class FloatRegOperand(Operand):
width = 0
if (self.ctype == 'float'):
width = 32
- func = 'setFloatReg'
+ func = 'setFloatRegOperand'
elif (self.ctype == 'double'):
width = 64
- func = 'setFloatReg'
+ func = 'setFloatRegOperand'
elif (self.ctype == 'uint32_t'):
- func = 'setFloatRegBits'
+ func = 'setFloatRegOperandBits'
width = 32
elif (self.ctype == 'uint64_t'):
- func = 'setFloatRegBits'
+ func = 'setFloatRegOperandBits'
width = 64
else:
- func = 'setFloatRegBits'
+ func = 'setFloatRegOperandBits'
final_ctype = 'uint%d_t' % self.dflt_size
if (self.size != self.dflt_size and self.is_signed):
final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index cdb892b3f..153f3f949 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -99,7 +99,7 @@ output exec {{
int size = sizeof(src_op) * 8;
for (int i = 0; i < inst->numSrcRegs(); i++) {
- uint64_t src_bits = xc->readFloatRegBits(inst, 0, size);
+ uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size);
if (isNan(&src_bits, size) ) {
if (isSnan(&src_bits, size)) {
@@ -113,7 +113,7 @@ output exec {{
mips_nan = src_bits;
}
- xc->setFloatRegBits(inst, 0, mips_nan, size);
+ xc->setFloatRegOperandBits(inst, 0, mips_nan, size);
if (traceData) { traceData->setData(mips_nan); }
return true;
}
@@ -139,7 +139,7 @@ output exec {{
}
//Set value to QNAN
- cpu->setFloatRegBits(inst, 0, mips_nan, size);
+ cpu->setFloatRegOperandBits(inst, 0, mips_nan, size);
//Read FCSR from FloatRegFile
uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
diff --git a/src/arch/mips/mmaped_ipr.hh b/src/arch/mips/mmaped_ipr.hh
index 041c76fdc..fa82a645c 100644
--- a/src/arch/mips/mmaped_ipr.hh
+++ b/src/arch/mips/mmaped_ipr.hh
@@ -37,8 +37,10 @@
* ISA-specific helper functions for memory mapped IPR accesses.
*/
+#include "base/misc.hh"
#include "mem/packet.hh"
+class ThreadContext;
namespace MipsISA
{
@@ -48,7 +50,6 @@ handleIprRead(ThreadContext *xc, Packet *pkt)
panic("No implementation for handleIprRead in MIPS\n");
}
-
inline Tick
handleIprWrite(ThreadContext *xc, Packet *pkt)
{
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index 5bc11aae6..53559c072 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -341,7 +341,6 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
case MISCREG_SOFTINT:
case MISCREG_TICK_CMPR:
case MISCREG_STICK_CMPR:
- case MISCREG_HPSTATE:
case MISCREG_HINTP:
case MISCREG_HTSTATE:
case MISCREG_HTBA:
@@ -357,9 +356,16 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
#if FULL_SYSTEM
+ case MISCREG_HPSTATE:
return readFSRegWithEffect(miscReg, tc);
#else
- panic("Accessing Fullsystem register is SE mode\n");
+ case MISCREG_HPSTATE:
+ //HPSTATE is special because because sometimes in privilege checks for instructions
+ //it will read HPSTATE to make sure the priv. level is ok
+ //So, we'll just have to tell it it isn't, instead of panicing.
+ return 0;
+
+ panic("Accessing Fullsystem register %s in SE mode\n",getMiscRegName(miscReg));
#endif
}
@@ -633,7 +639,6 @@ void MiscRegFile::setRegWithEffect(int miscReg,
case MISCREG_SOFTINT:
case MISCREG_TICK_CMPR:
case MISCREG_STICK_CMPR:
- case MISCREG_HPSTATE:
case MISCREG_HINTP:
case MISCREG_HTSTATE:
case MISCREG_HTBA:
@@ -649,10 +654,15 @@ void MiscRegFile::setRegWithEffect(int miscReg,
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
#if FULL_SYSTEM
+ case MISCREG_HPSTATE:
setFSRegWithEffect(miscReg, val, tc);
return;
#else
- panic("Accessing Fullsystem register is SE mode\n");
+ case MISCREG_HPSTATE:
+ //HPSTATE is special because normal trap processing saves HPSTATE when
+ //it goes into a trap, and restores it when it returns.
+ return;
+ panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val);
#endif
}
setReg(miscReg, val);
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 37d384473..675287d18 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -45,7 +45,7 @@ namespace SparcISA
{
TLB::TLB(const std::string &name, int s)
- : SimObject(name), size(s)
+ : SimObject(name), size(s), usedEntries(0), cacheValid(false)
{
// To make this work you'll have to change the hypervisor and OS
if (size > 64)
@@ -79,6 +79,8 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real,
TlbEntry *new_entry = NULL;
int x;
+ cacheValid = false;
+
DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d\n",
va, PTE.paddr(), partition_id, context_id, (int)real);
@@ -194,6 +196,8 @@ TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
TlbRange tr;
MapIter i;
+ cacheValid = false;
+
// Assemble full address structure
tr.va = va;
tr.size = va + MachineBytes;
@@ -217,6 +221,7 @@ void
TLB::demapContext(int partition_id, int context_id)
{
int x;
+ cacheValid = false;
for (x = 0; x < size; x++) {
if (tlb[x].range.contextId == context_id &&
tlb[x].range.partitionId == partition_id) {
@@ -234,6 +239,7 @@ void
TLB::demapAll(int partition_id)
{
int x;
+ cacheValid = false;
for (x = 0; x < size; x++) {
if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
tlb[x].valid = false;
@@ -250,6 +256,8 @@ void
TLB::invalidateAll()
{
int x;
+ cacheValid = false;
+
for (x = 0; x < size; x++) {
tlb[x].valid = false;
}
@@ -337,7 +345,7 @@ DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
}
- void
+void
DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
{
TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
@@ -350,6 +358,29 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
{
uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
+ Addr vaddr = req->getVaddr();
+ TlbEntry *e;
+
+ assert(req->getAsi() == ASI_IMPLICIT);
+
+ DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
+ vaddr, req->getSize());
+
+ // Be fast if we can!
+ if (cacheValid && cacheState == tlbdata) {
+ if (cacheEntry) {
+ if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
+ cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
+ req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) |
+ vaddr & cacheEntry->pte.size()-1 );
+ return NoFault;
+ }
+ } else {
+ req->setPaddr(vaddr & PAddrImplMask);
+ return NoFault;
+ }
+ }
+
bool hpriv = bits(tlbdata,0,0);
bool red = bits(tlbdata,1,1);
bool priv = bits(tlbdata,2,2);
@@ -359,21 +390,14 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
int part_id = bits(tlbdata,15,8);
int tl = bits(tlbdata,18,16);
int pri_context = bits(tlbdata,47,32);
-
- Addr vaddr = req->getVaddr();
int context;
ContextType ct;
int asi;
bool real = false;
- TlbEntry *e;
- DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
- vaddr, req->getSize());
DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
priv, hpriv, red, lsu_im, part_id);
- assert(req->getAsi() == ASI_IMPLICIT);
-
if (tl > 0) {
asi = ASI_N;
ct = Nucleus;
@@ -385,12 +409,15 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
}
if ( hpriv || red ) {
- req->setPaddr(req->getVaddr() & PAddrImplMask);
+ cacheValid = true;
+ cacheState = tlbdata;
+ cacheEntry = NULL;
+ req->setPaddr(vaddr & PAddrImplMask);
return NoFault;
}
- // If the asi is unaligned trap
- if (vaddr & req->getSize()-1) {
+ // If the access is unaligned trap
+ if (vaddr & 0x3) {
writeSfsr(tc, false, ct, false, OtherFault, asi);
return new MemAddressNotAligned;
}
@@ -404,7 +431,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
}
if (!lsu_im) {
- e = lookup(req->getVaddr(), part_id, true);
+ e = lookup(vaddr, part_id, true);
real = true;
context = 0;
} else {
@@ -426,9 +453,14 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
return new InstructionAccessException;
}
+ // cache translation date for next translation
+ cacheValid = true;
+ cacheState = tlbdata;
+ cacheEntry = e;
+
req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
- req->getVaddr() & e->pte.size()-1 );
- DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr());
+ vaddr & e->pte.size()-1 );
+ DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
return NoFault;
}
@@ -439,8 +471,40 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
{
/* @todo this could really use some profiling and fixing to make it faster! */
uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
-
+ Addr vaddr = req->getVaddr();
+ Addr size = req->getSize();
+ ASI asi;
+ asi = (ASI)req->getAsi();
+ bool implicit = false;
bool hpriv = bits(tlbdata,0,0);
+
+ DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
+ vaddr, size, asi);
+
+ if (asi == ASI_IMPLICIT)
+ implicit = true;
+
+ if (hpriv && implicit) {
+ req->setPaddr(vaddr & PAddrImplMask);
+ return NoFault;
+ }
+
+ // Be fast if we can!
+ if (cacheValid && cacheState == tlbdata) {
+ if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
+ cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) {
+ req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
+ vaddr & cacheEntry[0]->pte.size()-1 );
+ return NoFault;
+ }
+ if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
+ cacheEntry[1]->range.va + cacheEntry[1]->range.size >= vaddr) {
+ req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
+ vaddr & cacheEntry[1]->pte.size()-1 );
+ return NoFault;
+ }
+ }
+
bool red = bits(tlbdata,1,1);
bool priv = bits(tlbdata,2,2);
bool addr_mask = bits(tlbdata,3,3);
@@ -451,23 +515,14 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
int pri_context = bits(tlbdata,47,32);
int sec_context = bits(tlbdata,47,32);
- bool implicit = false;
bool real = false;
- Addr vaddr = req->getVaddr();
- Addr size = req->getSize();
ContextType ct = Primary;
int context = 0;
- ASI asi;
TlbEntry *e;
- asi = (ASI)req->getAsi();
- DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
- vaddr, size, asi);
DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
priv, hpriv, red, lsu_dm, part_id);
- if (asi == ASI_IMPLICIT)
- implicit = true;
if (implicit) {
if (tl > 0) {
@@ -562,11 +617,11 @@ continueDtbFlow:
};
if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
- req->setPaddr(req->getVaddr() & PAddrImplMask);
+ req->setPaddr(vaddr & PAddrImplMask);
return NoFault;
}
- e = lookup(req->getVaddr(), part_id, real, context);
+ e = lookup(vaddr, part_id, real, context);
if (e == NULL || !e->valid) {
tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS,
@@ -599,9 +654,21 @@ continueDtbFlow:
return new DataAccessException;
}
+ // cache translation date for next translation
+ cacheValid = true;
+ cacheState = tlbdata;
+ if (cacheEntry[0] != e && cacheEntry[1] != e) {
+ cacheEntry[1] = cacheEntry[0];
+ cacheEntry[0] = e;
+ cacheAsi[1] = cacheAsi[0];
+ cacheAsi[0] = asi;
+ if (implicit)
+ cacheAsi[0] = (ASI)0;
+ }
+
req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
- req->getVaddr() & e->pte.size()-1);
- DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr());
+ vaddr & e->pte.size()-1);
+ DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
return NoFault;
/** Normal flow ends here. */
@@ -773,8 +840,6 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
data = mbits(tsbtemp,63,13);
data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
- warn("base addr: %#X tag access: %#X page size: %#X tsb size: %#X\n",
- bits(tsbtemp,63,13), temp, bits(cnftemp,2,0), bits(tsbtemp,3,0));
pkt->set(data);
break;
case ASI_DMMU_TSB_PS1_PTR_REG:
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index b35f472cf..a6e6a8bd3 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -31,6 +31,7 @@
#ifndef __ARCH_SPARC_TLB_HH__
#define __ARCH_SPARC_TLB_HH__
+#include "arch/sparc/asi.hh"
#include "arch/sparc/tlb_map.hh"
#include "base/misc.hh"
#include "mem/request.hh"
@@ -54,6 +55,9 @@ class TLB : public SimObject
int size;
int usedEntries;
+ uint64_t cacheState;
+ bool cacheValid;
+
enum FaultTypes {
OtherFault = 0,
PrivViolation = 0x1,
@@ -131,6 +135,7 @@ class ITB : public TLB
public:
ITB(const std::string &name, int size) : TLB(name, size)
{
+ cacheEntry = NULL;
}
Fault translate(RequestPtr &req, ThreadContext *tc);
@@ -138,6 +143,7 @@ class ITB : public TLB
void writeSfsr(ThreadContext *tc, bool write, ContextType ct,
bool se, FaultTypes ft, int asi);
void writeTagAccess(ThreadContext *tc, Addr va, int context);
+ TlbEntry *cacheEntry;
friend class DTB;
};
@@ -146,6 +152,8 @@ class DTB : public TLB
public:
DTB(const std::string &name, int size) : TLB(name, size)
{
+ cacheEntry[0] = NULL;
+ cacheEntry[1] = NULL;
}
Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
@@ -157,7 +165,8 @@ class DTB : public TLB
bool se, FaultTypes ft, int asi);
void writeTagAccess(ThreadContext *tc, Addr va, int context);
-
+ TlbEntry *cacheEntry[2];
+ ASI cacheAsi[2];
};
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-24 21:11:13 +0000