diff options
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/alpha/kernel_stats.hh | 12 | ||||
-rw-r--r-- | src/arch/alpha/tlb.hh | 22 | ||||
-rw-r--r-- | src/arch/mips/tlb.hh | 16 |
3 files changed, 25 insertions, 25 deletions
diff --git a/src/arch/alpha/kernel_stats.hh b/src/arch/alpha/kernel_stats.hh index aab96b150..837269309 100644 --- a/src/arch/alpha/kernel_stats.hh +++ b/src/arch/alpha/kernel_stats.hh @@ -62,15 +62,15 @@ class Statistics : public ::Kernel::Statistics void changeMode(cpu_mode newmode, ThreadContext *tc); private: - Stats::Vector<> _callpal; -// Stats::Vector<> _faults; + Stats::Vector _callpal; +// Stats::Vector _faults; - Stats::Vector<> _mode; - Stats::Vector<> _modeGood; + Stats::Vector _mode; + Stats::Vector _modeGood; Stats::Formula _modeFraction; - Stats::Vector<> _modeTicks; + Stats::Vector _modeTicks; - Stats::Scalar<> _swap_context; + Stats::Scalar _swap_context; public: Statistics(System *system); diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh index 877533797..643889534 100644 --- a/src/arch/alpha/tlb.hh +++ b/src/arch/alpha/tlb.hh @@ -121,9 +121,9 @@ class TLB : public BaseTLB class ITB : public TLB { protected: - mutable Stats::Scalar<> hits; - mutable Stats::Scalar<> misses; - mutable Stats::Scalar<> acv; + mutable Stats::Scalar hits; + mutable Stats::Scalar misses; + mutable Stats::Scalar acv; mutable Stats::Formula accesses; public: @@ -139,14 +139,14 @@ class ITB : public TLB class DTB : public TLB { protected: - mutable Stats::Scalar<> read_hits; - mutable Stats::Scalar<> read_misses; - mutable Stats::Scalar<> read_acv; - mutable Stats::Scalar<> read_accesses; - mutable Stats::Scalar<> write_hits; - mutable Stats::Scalar<> write_misses; - mutable Stats::Scalar<> write_acv; - mutable Stats::Scalar<> write_accesses; + mutable Stats::Scalar read_hits; + mutable Stats::Scalar read_misses; + mutable Stats::Scalar read_acv; + mutable Stats::Scalar read_accesses; + mutable Stats::Scalar write_hits; + mutable Stats::Scalar write_misses; + mutable Stats::Scalar write_acv; + mutable Stats::Scalar write_accesses; Stats::Formula hits; Stats::Formula misses; Stats::Formula acv; diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh index 1ab9d77e5..dc0babf9a 100644 --- a/src/arch/mips/tlb.hh +++ b/src/arch/mips/tlb.hh @@ -96,14 +96,14 @@ class TLB : public BaseTLB void nextnlu() { if (++nlu >= size) nlu = 0; } MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const; - mutable Stats::Scalar<> read_hits; - mutable Stats::Scalar<> read_misses; - mutable Stats::Scalar<> read_acv; - mutable Stats::Scalar<> read_accesses; - mutable Stats::Scalar<> write_hits; - mutable Stats::Scalar<> write_misses; - mutable Stats::Scalar<> write_acv; - mutable Stats::Scalar<> write_accesses; + mutable Stats::Scalar read_hits; + mutable Stats::Scalar read_misses; + mutable Stats::Scalar read_acv; + mutable Stats::Scalar read_accesses; + mutable Stats::Scalar write_hits; + mutable Stats::Scalar write_misses; + mutable Stats::Scalar write_acv; + mutable Stats::Scalar write_accesses; Stats::Formula hits; Stats::Formula misses; Stats::Formula invalids; |