diff options
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/alpha/isa.cc | 2 | ||||
-rw-r--r-- | src/arch/alpha/isa.hh | 2 | ||||
-rw-r--r-- | src/arch/mips/isa.cc | 4 | ||||
-rw-r--r-- | src/arch/mips/isa.hh | 4 | ||||
-rw-r--r-- | src/arch/power/isa.hh | 2 | ||||
-rw-r--r-- | src/arch/sparc/isa.cc | 2 | ||||
-rw-r--r-- | src/arch/sparc/isa.hh | 2 | ||||
-rw-r--r-- | src/arch/x86/isa.cc | 2 | ||||
-rw-r--r-- | src/arch/x86/isa.hh | 2 |
9 files changed, 11 insertions, 11 deletions
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc index 95dfdedd6..20f039166 100644 --- a/src/arch/alpha/isa.cc +++ b/src/arch/alpha/isa.cc @@ -74,7 +74,7 @@ ISA::unserialize(Checkpoint *cp, const std::string §ion) MiscReg -ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) +ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const { switch (misc_reg) { case MISCREG_FPCR: diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh index 36515b520..52e4e98be 100644 --- a/src/arch/alpha/isa.hh +++ b/src/arch/alpha/isa.hh @@ -73,7 +73,7 @@ namespace AlphaISA public: - MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0); + MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); void setMiscRegNoEffect(int misc_reg, const MiscReg &val, diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc index 164f10d5d..a37f523d9 100644 --- a/src/arch/mips/isa.cc +++ b/src/arch/mips/isa.cc @@ -410,14 +410,14 @@ ISA::configCP() } inline unsigned -ISA::getVPENum(ThreadID tid) +ISA::getVPENum(ThreadID tid) const { TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid]; return tcBind.curVPE; } MiscReg -ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) +ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const { unsigned reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh index fea3f00ca..feb55e473 100644 --- a/src/arch/mips/isa.hh +++ b/src/arch/mips/isa.hh @@ -76,7 +76,7 @@ namespace MipsISA void configCP(); - unsigned getVPENum(ThreadID tid); + unsigned getVPENum(ThreadID tid) const; ////////////////////////////////////////////////////////// // @@ -87,7 +87,7 @@ namespace MipsISA //@TODO: MIPS MT's register view automatically connects // Status to TCStatus depending on current thread void updateCP0ReadView(int misc_reg, ThreadID tid) { } - MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0); + MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; //template <class TC> MiscReg readMiscReg(int misc_reg, diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh index d19410037..aaf5bd92a 100644 --- a/src/arch/power/isa.hh +++ b/src/arch/power/isa.hh @@ -61,7 +61,7 @@ class ISA : public SimObject } MiscReg - readMiscRegNoEffect(int misc_reg) + readMiscRegNoEffect(int misc_reg) const { fatal("Power does not currently have any misc regs defined\n"); return dummy; diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc index 4daf8775b..c9a3a33b4 100644 --- a/src/arch/sparc/isa.cc +++ b/src/arch/sparc/isa.cc @@ -173,7 +173,7 @@ ISA::clear() } MiscReg -ISA::readMiscRegNoEffect(int miscReg) +ISA::readMiscRegNoEffect(int miscReg) const { // The three miscRegs are moved up from the switch statement diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh index 536deb69c..4551cf3c1 100644 --- a/src/arch/sparc/isa.hh +++ b/src/arch/sparc/isa.hh @@ -183,7 +183,7 @@ class ISA : public SimObject public: - MiscReg readMiscRegNoEffect(int miscReg); + MiscReg readMiscRegNoEffect(int miscReg) const; MiscReg readMiscReg(int miscReg, ThreadContext *tc); void setMiscRegNoEffect(int miscReg, const MiscReg val); diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc index f65bc2392..f2d3ce42a 100644 --- a/src/arch/x86/isa.cc +++ b/src/arch/x86/isa.cc @@ -124,7 +124,7 @@ ISA::params() const } MiscReg -ISA::readMiscRegNoEffect(int miscReg) +ISA::readMiscRegNoEffect(int miscReg) const { // Make sure we're not dealing with an illegal control register. // Instructions should filter out these indexes, and nothing else should diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh index 3ca771c61..a82b4ae2f 100644 --- a/src/arch/x86/isa.hh +++ b/src/arch/x86/isa.hh @@ -63,7 +63,7 @@ namespace X86ISA ISA(Params *p); const Params *params() const; - MiscReg readMiscRegNoEffect(int miscReg); + MiscReg readMiscRegNoEffect(int miscReg) const; MiscReg readMiscReg(int miscReg, ThreadContext *tc); void setMiscRegNoEffect(int miscReg, MiscReg val); |