diff options
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/tlb.cc | 16 | ||||
| -rw-r--r-- | src/arch/arm/tlb.hh | 1 | ||||
| -rw-r--r-- | src/arch/generic/memhelpers.hh | 1 | ||||
| -rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 3 | ||||
| -rw-r--r-- | src/arch/x86/isa/insts/system/msrs.py | 10 | ||||
| -rw-r--r-- | src/arch/x86/isa/macroop.isa | 11 | ||||
| -rw-r--r-- | src/arch/x86/tlb.cc | 14 | ||||
| -rw-r--r-- | src/arch/x86/tlb.hh | 1 |
8 files changed, 56 insertions, 1 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 5f104e96d..fab26d8cb 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -535,6 +535,11 @@ TLB::regStats() .name(name() + ".prefetch_faults") .desc("Number of TLB faults due to prefetch") ; + + specTLBMisses + .name(name() + ".spec_tlb_misses") + .desc("Number of TLB misses from a speculative mem instructions") + ; domainFaults .name(name() + ".domain_faults") @@ -1423,6 +1428,17 @@ TLB::getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode, vaddr_tainted, ArmFault::PrefetchTLBMiss, isStage2); } + if (req->isSpec()) { + // if the request is a prefetch don't attempt to fill the TLB or go + // any further with the memory access (here we can safely use the + // fault status for the short desc. format in all cases) + specTLBMisses++; + //FIXME: currently resue the prefetch tlbmiss fault + //do not want to introduce new fault declaration + return std::make_shared<PrefetchAbort>( + vaddr_tainted, ArmFault::PrefetchTLBMiss, isStage2); + } + if (is_fetch) instMisses++; else if (is_write) diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 212a79f79..5f92a3e8a 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -169,6 +169,7 @@ class TLB : public BaseTLB mutable Stats::Scalar flushedEntries; mutable Stats::Scalar alignFaults; mutable Stats::Scalar prefetchFaults; + mutable Stats::Scalar specTLBMisses; mutable Stats::Scalar domainFaults; mutable Stats::Scalar permsFaults; diff --git a/src/arch/generic/memhelpers.hh b/src/arch/generic/memhelpers.hh index 35e666b92..0a38b780c 100644 --- a/src/arch/generic/memhelpers.hh +++ b/src/arch/generic/memhelpers.hh @@ -53,6 +53,7 @@ /// Initiate a read from memory in timing mode. Note that the 'mem' /// parameter is unused; only the type of that parameter is used /// to determine the size of the access. +// XC: executeContextPtr [mengjia] template <class XC, class MemT> Fault initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr, diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index aa60e4c48..bc8edf416 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -133,7 +133,8 @@ 0x7: decode MODRM_MOD { 0x3: decode MODRM_RM { 0x0: Inst::SWAPGS(); - 0x1: rdtscp(); + 0x1: Inst::RDTSCP(); + //rdtscp(); default: Inst::UD2(); } default: Inst::INVLPG(M); diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py index d0e2675de..f269742dd 100644 --- a/src/arch/x86/isa/insts/system/msrs.py +++ b/src/arch/x86/isa/insts/system/msrs.py @@ -65,4 +65,14 @@ def macroop RDTSC srli t1, t1, 32, dataSize=8 mov rdx, rdx, t1, dataSize=4 }; + + +def macroop RDTSCP +{ + .block + rdtsc t1 + mov rax, rax, t1, dataSize=4 + srli t1, t1, 32, dataSize=8 + mov rdx, rdx, t1, dataSize=4 +}; ''' diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index 3a1a84a7d..aff0b942c 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -146,6 +146,9 @@ let {{ self.adjust_disp += val def serializing(self): self.serializing = True + # define directive [mengjia] + def block(self): + self.block = True def function_call(self): self.function_call = True @@ -159,6 +162,8 @@ let {{ "adjust_imm" : self.adjustImm, "adjust_disp" : self.adjustDisp, "serializing" : self.serializing, + # add directives block [mengjia] + "block" : self.block, "function_call" : self.function_call, "function_return" : self.function_return } @@ -176,6 +181,8 @@ let {{ adjustedDisp = adjustedDisp; ''' self.serializing = False + # initialize as false [mengjia] + self.block = False self.function_call = False self.function_return = False @@ -212,6 +219,10 @@ let {{ if self.serializing: flags.append("IsSerializing") flags.append("IsSerializeAfter") + # add new attribute for block [mengjia] + if self.block: + flags.append("IsBlock") + flags.append("IsSerializeBefore") if self.function_call: flags.append("IsCall") diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index a3aec1676..248f929f9 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -338,6 +338,17 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, wrAccesses++; } if (!entry) { + if(req->isSpec()){ + // [InvisiSpec] do not perform TLB fill for + // speculative load + specMisses++; + DPRINTF(TLB, "Get a TLB miss for a speculative load " + "address %#x at pc %#x.\n", + vaddr, tc->instAddr()); + //FIXME: currently reuse the GeneralProtection fault + //instead of creating new faults + return std::make_shared<GeneralProtection>(0); + } DPRINTF(TLB, "Handling a TLB miss for " "address %#x at pc %#x.\n", vaddr, tc->instAddr()); @@ -470,6 +481,9 @@ TLB::regStats() .name(name() + ".wrMisses") .desc("TLB misses on write requests"); + specMisses + .name(name() + ".spec_tlb_misses") + .desc("TLB misses on speculative memory requests"); } void diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index 08804a455..9e9c8fa05 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -105,6 +105,7 @@ namespace X86ISA Stats::Scalar wrAccesses; Stats::Scalar rdMisses; Stats::Scalar wrMisses; + Stats::Scalar specMisses; Fault translateInt(RequestPtr req, ThreadContext *tc); |