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-rw-r--r--src/arch/alpha/AlphaInterrupts.py1
-rw-r--r--src/arch/alpha/AlphaSystem.py4
-rw-r--r--src/arch/alpha/AlphaTLB.py1
-rw-r--r--src/arch/arm/ArmInterrupts.py1
-rw-r--r--src/arch/arm/ArmNativeTrace.py1
-rw-r--r--src/arch/arm/ArmSystem.py2
-rw-r--r--src/arch/arm/ArmTLB.py2
-rw-r--r--src/arch/mips/MipsInterrupts.py1
-rw-r--r--src/arch/mips/MipsSystem.py3
-rw-r--r--src/arch/mips/MipsTLB.py1
-rw-r--r--src/arch/power/PowerInterrupts.py1
-rw-r--r--src/arch/power/PowerTLB.py1
-rw-r--r--src/arch/sparc/SparcInterrupts.py1
-rw-r--r--src/arch/sparc/SparcNativeTrace.py1
-rw-r--r--src/arch/sparc/SparcSystem.py1
-rw-r--r--src/arch/sparc/SparcTLB.py1
-rw-r--r--src/arch/x86/X86LocalApic.py1
-rw-r--r--src/arch/x86/X86NativeTrace.py1
-rw-r--r--src/arch/x86/X86System.py2
-rw-r--r--src/arch/x86/X86TLB.py2
-rw-r--r--src/arch/x86/bios/ACPI.py4
-rw-r--r--src/arch/x86/bios/E820.py2
-rw-r--r--src/arch/x86/bios/IntelMP.py12
-rw-r--r--src/arch/x86/bios/SMBios.py3
24 files changed, 50 insertions, 0 deletions
diff --git a/src/arch/alpha/AlphaInterrupts.py b/src/arch/alpha/AlphaInterrupts.py
index ecfcf5c21..a75b11fc0 100644
--- a/src/arch/alpha/AlphaInterrupts.py
+++ b/src/arch/alpha/AlphaInterrupts.py
@@ -31,3 +31,4 @@ from m5.SimObject import SimObject
class AlphaInterrupts(SimObject):
type = 'AlphaInterrupts'
cxx_class = 'AlphaISA::Interrupts'
+ cxx_header = "arch/alpha/interrupts.hh"
diff --git a/src/arch/alpha/AlphaSystem.py b/src/arch/alpha/AlphaSystem.py
index fcbe81edd..2486ec059 100644
--- a/src/arch/alpha/AlphaSystem.py
+++ b/src/arch/alpha/AlphaSystem.py
@@ -32,6 +32,7 @@ from System import System
class AlphaSystem(System):
type = 'AlphaSystem'
+ cxx_header = "arch/alpha/system.hh"
console = Param.String("file that contains the console code")
pal = Param.String("file that contains palcode")
system_type = Param.UInt64("Type of system we are emulating")
@@ -40,6 +41,7 @@ class AlphaSystem(System):
class LinuxAlphaSystem(AlphaSystem):
type = 'LinuxAlphaSystem'
+ cxx_header = "arch/alpha/linux/system.hh"
system_type = 34
system_rev = 1 << 10
@@ -48,10 +50,12 @@ class LinuxAlphaSystem(AlphaSystem):
class FreebsdAlphaSystem(AlphaSystem):
type = 'FreebsdAlphaSystem'
+ cxx_header = "arch/alpha/freebsd/system.hh"
system_type = 34
system_rev = 1 << 10
class Tru64AlphaSystem(AlphaSystem):
type = 'Tru64AlphaSystem'
+ cxx_header = "arch/alpha/tru64/system.hh"
system_type = 12
system_rev = 2<<1
diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py
index 51f636ec2..8031c719f 100644
--- a/src/arch/alpha/AlphaTLB.py
+++ b/src/arch/alpha/AlphaTLB.py
@@ -34,6 +34,7 @@ from BaseTLB import BaseTLB
class AlphaTLB(BaseTLB):
type = 'AlphaTLB'
cxx_class = 'AlphaISA::TLB'
+ cxx_header = "arch/alpha/tlb.hh"
size = Param.Int("TLB size")
class AlphaDTB(AlphaTLB):
diff --git a/src/arch/arm/ArmInterrupts.py b/src/arch/arm/ArmInterrupts.py
index f21d49e95..68a58958d 100644
--- a/src/arch/arm/ArmInterrupts.py
+++ b/src/arch/arm/ArmInterrupts.py
@@ -31,3 +31,4 @@ from m5.SimObject import SimObject
class ArmInterrupts(SimObject):
type = 'ArmInterrupts'
cxx_class = 'ArmISA::Interrupts'
+ cxx_header = "arch/arm/interrupts.hh"
diff --git a/src/arch/arm/ArmNativeTrace.py b/src/arch/arm/ArmNativeTrace.py
index 0a76913e3..91da1ed76 100644
--- a/src/arch/arm/ArmNativeTrace.py
+++ b/src/arch/arm/ArmNativeTrace.py
@@ -33,5 +33,6 @@ from NativeTrace import NativeTrace
class ArmNativeTrace(NativeTrace):
type = 'ArmNativeTrace'
cxx_class = 'Trace::ArmNativeTrace'
+ cxx_header = "arch/arm/nativetrace.hh"
stop_on_pc_error = Param.Bool(True,
"Stop M5 if it and statetrace's pcs are different")
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 3ca9b8573..ce363865c 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -48,6 +48,7 @@ class ArmMachineType(Enum):
class ArmSystem(System):
type = 'ArmSystem'
+ cxx_header = "arch/arm/system.hh"
load_addr_mask = 0xffffffff
# 0x35 Implementor is '5' from "M5"
# 0x0 Variant
@@ -62,6 +63,7 @@ class ArmSystem(System):
class LinuxArmSystem(ArmSystem):
type = 'LinuxArmSystem'
+ cxx_header = "arch/arm/linux/system.hh"
load_addr_mask = 0x0fffffff
machine_type = Param.ArmMachineType('RealView_PBX',
"Machine id from http://www.arm.linux.org.uk/developer/machines/")
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index 0a931b7e5..c70dd80c8 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -45,6 +45,7 @@ from MemObject import MemObject
class ArmTableWalker(MemObject):
type = 'ArmTableWalker'
cxx_class = 'ArmISA::TableWalker'
+ cxx_header = "arch/arm/table_walker.hh"
port = MasterPort("Port for TableWalker to do walk the translation with")
sys = Param.System(Parent.any, "system object parameter")
num_squash_per_cycle = Param.Unsigned(2,
@@ -53,5 +54,6 @@ class ArmTableWalker(MemObject):
class ArmTLB(SimObject):
type = 'ArmTLB'
cxx_class = 'ArmISA::TLB'
+ cxx_header = "arch/arm/tlb.hh"
size = Param.Int(64, "TLB size")
walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
diff --git a/src/arch/mips/MipsInterrupts.py b/src/arch/mips/MipsInterrupts.py
index 06cd54263..9cde5daef 100644
--- a/src/arch/mips/MipsInterrupts.py
+++ b/src/arch/mips/MipsInterrupts.py
@@ -31,3 +31,4 @@ from m5.SimObject import SimObject
class MipsInterrupts(SimObject):
type = 'MipsInterrupts'
cxx_class = 'MipsISA::Interrupts'
+ cxx_header = 'arch/mips/interrupts.hh'
diff --git a/src/arch/mips/MipsSystem.py b/src/arch/mips/MipsSystem.py
index 4a0851eba..c6ceb71db 100644
--- a/src/arch/mips/MipsSystem.py
+++ b/src/arch/mips/MipsSystem.py
@@ -36,6 +36,7 @@ from System import System
class MipsSystem(System):
type = 'MipsSystem'
+ cxx_header = 'arch/mips/system.hh'
console = Param.String("file that contains the console code")
bare_iron = Param.Bool(False, "Using Bare Iron Mode?")
hex_file_name = Param.String("test.hex","hex file that contains [address,data] pairs")
@@ -45,6 +46,7 @@ class MipsSystem(System):
class LinuxMipsSystem(MipsSystem):
type = 'LinuxMipsSystem'
+ cxx_header = 'arch/mips/linux/system.hh'
system_type = 34
system_rev = 1 << 10
@@ -53,6 +55,7 @@ class LinuxMipsSystem(MipsSystem):
class BareIronMipsSystem(MipsSystem):
type = 'BareIronMipsSystem'
+ cxx_header = 'arch/mips/bare_iron/system.hh'
bare_iron = True
system_type = 34
system_rev = 1 << 10
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index 16cbe6879..c43cee717 100644
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -37,4 +37,5 @@ from BaseTLB import BaseTLB
class MipsTLB(BaseTLB):
type = 'MipsTLB'
cxx_class = 'MipsISA::TLB'
+ cxx_header = 'arch/mips/tlb.hh'
size = Param.Int(64, "TLB size")
diff --git a/src/arch/power/PowerInterrupts.py b/src/arch/power/PowerInterrupts.py
index 82d614077..2c6a5c2c3 100644
--- a/src/arch/power/PowerInterrupts.py
+++ b/src/arch/power/PowerInterrupts.py
@@ -31,3 +31,4 @@ from m5.SimObject import SimObject
class PowerInterrupts(SimObject):
type = 'PowerInterrupts'
cxx_class = 'PowerISA::Interrupts'
+ cxx_header = 'arch/power/interrupts.hh'
diff --git a/src/arch/power/PowerTLB.py b/src/arch/power/PowerTLB.py
index 36dff5333..ae6503a1f 100644
--- a/src/arch/power/PowerTLB.py
+++ b/src/arch/power/PowerTLB.py
@@ -34,4 +34,5 @@ from m5.params import *
class PowerTLB(SimObject):
type = 'PowerTLB'
cxx_class = 'PowerISA::TLB'
+ cxx_header = 'arch/power/tlb.hh'
size = Param.Int(64, "TLB size")
diff --git a/src/arch/sparc/SparcInterrupts.py b/src/arch/sparc/SparcInterrupts.py
index 2cc964c2d..c11176164 100644
--- a/src/arch/sparc/SparcInterrupts.py
+++ b/src/arch/sparc/SparcInterrupts.py
@@ -31,3 +31,4 @@ from m5.SimObject import SimObject
class SparcInterrupts(SimObject):
type = 'SparcInterrupts'
cxx_class = 'SparcISA::Interrupts'
+ cxx_header = 'arch/sparc/interrupts.hh'
diff --git a/src/arch/sparc/SparcNativeTrace.py b/src/arch/sparc/SparcNativeTrace.py
index 0a92764ef..cdc34b541 100644
--- a/src/arch/sparc/SparcNativeTrace.py
+++ b/src/arch/sparc/SparcNativeTrace.py
@@ -33,3 +33,4 @@ from NativeTrace import NativeTrace
class SparcNativeTrace(NativeTrace):
type = 'SparcNativeTrace'
cxx_class = 'Trace::SparcNativeTrace'
+ cxx_header = 'arch/sparc/nativetrace.hh'
diff --git a/src/arch/sparc/SparcSystem.py b/src/arch/sparc/SparcSystem.py
index b0fddf311..9d8be5d06 100644
--- a/src/arch/sparc/SparcSystem.py
+++ b/src/arch/sparc/SparcSystem.py
@@ -33,6 +33,7 @@ from System import System
class SparcSystem(System):
type = 'SparcSystem'
+ cxx_header = 'arch/sparc/system.hh'
_rom_base = 0xfff0000000
_nvram_base = 0x1f11000000
_hypervisor_desc_base = 0x1f12080000
diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py
index 0c3fdc7fb..219f6842a 100644
--- a/src/arch/sparc/SparcTLB.py
+++ b/src/arch/sparc/SparcTLB.py
@@ -34,4 +34,5 @@ from BaseTLB import BaseTLB
class SparcTLB(BaseTLB):
type = 'SparcTLB'
cxx_class = 'SparcISA::TLB'
+ cxx_header = 'arch/sparc/tlb.hh'
size = Param.Int(64, "TLB size")
diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py
index 0bc36612d..5c14679c2 100644
--- a/src/arch/x86/X86LocalApic.py
+++ b/src/arch/x86/X86LocalApic.py
@@ -46,6 +46,7 @@ from Device import BasicPioDevice
class X86LocalApic(BasicPioDevice):
type = 'X86LocalApic'
cxx_class = 'X86ISA::Interrupts'
+ cxx_header = 'arch/x86/interrupts.hh'
int_master = MasterPort("Port for sending interrupt messages")
int_slave = SlavePort("Port for receiving interrupt messages")
int_latency = Param.Latency('1ns', \
diff --git a/src/arch/x86/X86NativeTrace.py b/src/arch/x86/X86NativeTrace.py
index cbed77f37..281a2df50 100644
--- a/src/arch/x86/X86NativeTrace.py
+++ b/src/arch/x86/X86NativeTrace.py
@@ -33,3 +33,4 @@ from NativeTrace import NativeTrace
class X86NativeTrace(NativeTrace):
type = 'X86NativeTrace'
cxx_class = 'Trace::X86NativeTrace'
+ cxx_header = 'arch/x86/nativetrace.hh'
diff --git a/src/arch/x86/X86System.py b/src/arch/x86/X86System.py
index 8b294fb86..02185b648 100644
--- a/src/arch/x86/X86System.py
+++ b/src/arch/x86/X86System.py
@@ -44,6 +44,7 @@ from System import System
class X86System(System):
type = 'X86System'
+ cxx_header = 'arch/x86/system.hh'
smbios_table = Param.X86SMBiosSMBiosTable(
X86SMBiosSMBiosTable(), 'table of smbios/dmi information')
intel_mp_pointer = Param.X86IntelMPFloatingPointer(
@@ -58,6 +59,7 @@ class X86System(System):
class LinuxX86System(X86System):
type = 'LinuxX86System'
+ cxx_header = 'arch/x86/linux/system.hh'
e820_table = Param.X86E820Table(
X86E820Table(), 'E820 map of physical memory')
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index 334d2a0cf..a08dbb138 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -44,12 +44,14 @@ from MemObject import MemObject
class X86PagetableWalker(MemObject):
type = 'X86PagetableWalker'
cxx_class = 'X86ISA::Walker'
+ cxx_header = 'arch/x86/pagetable_walker.hh'
port = MasterPort("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
class X86TLB(BaseTLB):
type = 'X86TLB'
cxx_class = 'X86ISA::TLB'
+ cxx_header = 'arch/x86/tlb.hh'
size = Param.Int(64, "TLB size")
walker = Param.X86PagetableWalker(\
X86PagetableWalker(), "page table walker")
diff --git a/src/arch/x86/bios/ACPI.py b/src/arch/x86/bios/ACPI.py
index 671ed902d..77de42f92 100644
--- a/src/arch/x86/bios/ACPI.py
+++ b/src/arch/x86/bios/ACPI.py
@@ -41,6 +41,7 @@ from m5.SimObject import SimObject
class X86ACPISysDescTable(SimObject):
type = 'X86ACPISysDescTable'
cxx_class = 'X86ISA::ACPI::SysDescTable'
+ cxx_header = 'arch/x86/bios/acpi.hh'
abstract = True
oem_id = Param.String('', 'string identifying the oem')
@@ -55,12 +56,14 @@ class X86ACPISysDescTable(SimObject):
class X86ACPIRSDT(X86ACPISysDescTable):
type = 'X86ACPIRSDT'
cxx_class = 'X86ISA::ACPI::RSDT'
+ cxx_header = 'arch/x86/bios/acpi.hh'
entries = VectorParam.X86ACPISysDescTable([], 'system description tables')
class X86ACPIXSDT(X86ACPISysDescTable):
type = 'X86ACPIXSDT'
cxx_class = 'X86ISA::ACPI::XSDT'
+ cxx_header = 'arch/x86/bios/acpi.hh'
entries = VectorParam.X86ACPISysDescTable([], 'system description tables')
@@ -68,6 +71,7 @@ class X86ACPIXSDT(X86ACPISysDescTable):
class X86ACPIRSDP(SimObject):
type = 'X86ACPIRSDP'
cxx_class = 'X86ISA::ACPI::RSDP'
+ cxx_header = 'arch/x86/bios/acpi.hh'
oem_id = Param.String('', 'string identifying the oem')
# Because 0 encodes ACPI 1.0, 2 encodes ACPI 3.0, the version implemented
diff --git a/src/arch/x86/bios/E820.py b/src/arch/x86/bios/E820.py
index 78b5faee0..9fa18edbd 100644
--- a/src/arch/x86/bios/E820.py
+++ b/src/arch/x86/bios/E820.py
@@ -41,6 +41,7 @@ from m5.SimObject import SimObject
class X86E820Entry(SimObject):
type = 'X86E820Entry'
cxx_class = 'X86ISA::E820Entry'
+ cxx_header = 'arch/x86/bios/e820.hh'
addr = Param.Addr(0, 'address of the beginning of the region')
size = Param.MemorySize('0B', 'size of the region')
@@ -49,5 +50,6 @@ class X86E820Entry(SimObject):
class X86E820Table(SimObject):
type = 'X86E820Table'
cxx_class = 'X86ISA::E820Table'
+ cxx_header = 'arch/x86/bios/e820.hh'
entries = VectorParam.X86E820Entry('entries for the e820 table')
diff --git a/src/arch/x86/bios/IntelMP.py b/src/arch/x86/bios/IntelMP.py
index 713f62960..21f93eaad 100644
--- a/src/arch/x86/bios/IntelMP.py
+++ b/src/arch/x86/bios/IntelMP.py
@@ -41,6 +41,7 @@ from m5.SimObject import SimObject
class X86IntelMPFloatingPointer(SimObject):
type = 'X86IntelMPFloatingPointer'
cxx_class = 'X86ISA::IntelMP::FloatingPointer'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
# The minor revision of the spec to support. The major version is assumed
# to be 1 in accordance with the spec.
@@ -53,6 +54,7 @@ class X86IntelMPFloatingPointer(SimObject):
class X86IntelMPConfigTable(SimObject):
type = 'X86IntelMPConfigTable'
cxx_class = 'X86ISA::IntelMP::ConfigTable'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported')
oem_id = Param.String("", 'system manufacturer')
@@ -80,16 +82,19 @@ class X86IntelMPConfigTable(SimObject):
class X86IntelMPBaseConfigEntry(SimObject):
type = 'X86IntelMPBaseConfigEntry'
cxx_class = 'X86ISA::IntelMP::BaseConfigEntry'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
abstract = True
class X86IntelMPExtConfigEntry(SimObject):
type = 'X86IntelMPExtConfigEntry'
cxx_class = 'X86ISA::IntelMP::ExtConfigEntry'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
abstract = True
class X86IntelMPProcessor(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPProcessor'
cxx_class = 'X86ISA::IntelMP::Processor'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
local_apic_id = Param.UInt8(0, 'local APIC id')
local_apic_version = Param.UInt8(0,
@@ -106,6 +111,7 @@ class X86IntelMPProcessor(X86IntelMPBaseConfigEntry):
class X86IntelMPBus(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPBus'
cxx_class = 'X86ISA::IntelMP::Bus'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
bus_id = Param.UInt8(0, 'bus id assigned by the bios')
bus_type = Param.String("", 'string that identify the bus type')
@@ -118,6 +124,7 @@ class X86IntelMPBus(X86IntelMPBaseConfigEntry):
class X86IntelMPIOAPIC(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPIOAPIC'
cxx_class = 'X86ISA::IntelMP::IOAPIC'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
id = Param.UInt8(0, 'id of this APIC')
version = Param.UInt8(0, 'bits 0-7 of the version register')
@@ -148,6 +155,7 @@ class X86IntelMPTriggerMode(Enum):
class X86IntelMPIOIntAssignment(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPIOIntAssignment'
cxx_class = 'X86ISA::IntelMP::IOIntAssignment'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt')
@@ -167,6 +175,7 @@ class X86IntelMPIOIntAssignment(X86IntelMPBaseConfigEntry):
class X86IntelMPLocalIntAssignment(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPLocalIntAssignment'
cxx_class = 'X86ISA::IntelMP::LocalIntAssignment'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt')
@@ -192,6 +201,7 @@ class X86IntelMPAddressType(Enum):
class X86IntelMPAddrSpaceMapping(X86IntelMPExtConfigEntry):
type = 'X86IntelMPAddrSpaceMapping'
cxx_class = 'X86ISA::IntelMP::AddrSpaceMapping'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
bus_id = Param.UInt8(0, 'id of the bus the address space is mapped to')
address_type = Param.X86IntelMPAddressType('IOAddress',
@@ -202,6 +212,7 @@ class X86IntelMPAddrSpaceMapping(X86IntelMPExtConfigEntry):
class X86IntelMPBusHierarchy(X86IntelMPExtConfigEntry):
type = 'X86IntelMPBusHierarchy'
cxx_class = 'X86ISA::IntelMP::BusHierarchy'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
bus_id = Param.UInt8(0, 'id of the bus being described')
subtractive_decode = Param.Bool(False,
@@ -216,6 +227,7 @@ class X86IntelMPRangeList(Enum):
class X86IntelMPCompatAddrSpaceMod(X86IntelMPExtConfigEntry):
type = 'X86IntelMPCompatAddrSpaceMod'
cxx_class = 'X86ISA::IntelMP::CompatAddrSpaceMod'
+ cxx_header = 'arch/x86/bios/intelmp.hh'
bus_id = Param.UInt8(0, 'id of the bus being described')
add = Param.Bool(False,
diff --git a/src/arch/x86/bios/SMBios.py b/src/arch/x86/bios/SMBios.py
index 8fd3d57d8..918d43c2e 100644
--- a/src/arch/x86/bios/SMBios.py
+++ b/src/arch/x86/bios/SMBios.py
@@ -41,6 +41,7 @@ from m5.SimObject import SimObject
class X86SMBiosSMBiosStructure(SimObject):
type = 'X86SMBiosSMBiosStructure'
cxx_class = 'X86ISA::SMBios::SMBiosStructure'
+ cxx_header = 'arch/x86/bios/smbios.hh'
abstract = True
class Characteristic(Enum):
@@ -93,6 +94,7 @@ class ExtCharacteristic(Enum):
class X86SMBiosBiosInformation(X86SMBiosSMBiosStructure):
type = 'X86SMBiosBiosInformation'
cxx_class = 'X86ISA::SMBios::BiosInformation'
+ cxx_header = 'arch/x86/bios/smbios.hh'
vendor = Param.String("", "vendor name string")
version = Param.String("", "version string")
@@ -115,6 +117,7 @@ class X86SMBiosBiosInformation(X86SMBiosSMBiosStructure):
class X86SMBiosSMBiosTable(SimObject):
type = 'X86SMBiosSMBiosTable'
cxx_class = 'X86ISA::SMBios::SMBiosTable'
+ cxx_header = 'arch/x86/bios/smbios.hh'
major_version = Param.UInt8(2, "major version number")
minor_version = Param.UInt8(5, "minor version number")
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-15 11:16:43 +0000