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-rw-r--r--src/arch/alpha/ev5.cc14
-rw-r--r--src/arch/alpha/floatregfile.hh4
-rw-r--r--src/arch/alpha/intregfile.hh4
-rw-r--r--src/arch/alpha/isa/fp.isa12
-rw-r--r--src/arch/alpha/tlb.cc8
-rw-r--r--src/arch/sparc/isa/base.isa70
-rw-r--r--src/arch/sparc/isa/formats/basic.isa33
-rw-r--r--src/arch/sparc/isa/formats/mem/basicmem.isa4
-rw-r--r--src/arch/sparc/isa/formats/mem/blockmem.isa2
-rw-r--r--src/arch/sparc/isa/formats/mem/swap.isa2
-rw-r--r--src/arch/sparc/isa/formats/micro.isa33
-rw-r--r--src/arch/sparc/isa/includes.isa12
-rw-r--r--src/arch/sparc/isa/operands.isa54
-rw-r--r--src/arch/sparc/process.cc1
-rw-r--r--src/arch/x86/process.cc1
15 files changed, 186 insertions, 68 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index ec5090eb8..86b8fd2d0 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -245,13 +245,13 @@ AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
{
AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating());
- retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
- retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
- retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
- retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
- retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
- retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
- retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
+ retval |= ((uint64_t)pte.ppn & ULL(0x7ffffff)) << 32;
+ retval |= ((uint64_t)pte.xre & ULL(0xf)) << 8;
+ retval |= ((uint64_t)pte.xwe & ULL(0xf)) << 12;
+ retval |= ((uint64_t)pte.fonr & ULL(0x1)) << 1;
+ retval |= ((uint64_t)pte.fonw & ULL(0x1))<< 2;
+ retval |= ((uint64_t)pte.asma & ULL(0x1)) << 4;
+ retval |= ((uint64_t)pte.asn & ULL(0x7f)) << 57;
}
break;
diff --git a/src/arch/alpha/floatregfile.hh b/src/arch/alpha/floatregfile.hh
index d289f5785..0c5fe17a7 100644
--- a/src/arch/alpha/floatregfile.hh
+++ b/src/arch/alpha/floatregfile.hh
@@ -35,7 +35,7 @@
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/types.hh"
-#include <string.h>
+#include <cstring>
#include <iostream>
class Checkpoint;
@@ -61,7 +61,7 @@ namespace AlphaISA
void unserialize(Checkpoint *cp, const std::string &section);
void clear()
- { bzero(d, sizeof(d)); }
+ { std::memset(d, 0, sizeof(d)); }
};
}
diff --git a/src/arch/alpha/intregfile.hh b/src/arch/alpha/intregfile.hh
index 0d65f69e0..dea160992 100644
--- a/src/arch/alpha/intregfile.hh
+++ b/src/arch/alpha/intregfile.hh
@@ -35,7 +35,7 @@
#include "arch/alpha/types.hh"
#include <iostream>
-#include <strings.h>
+#include <cstring>
class Checkpoint;
@@ -71,7 +71,7 @@ namespace AlphaISA
void unserialize(Checkpoint *cp, const std::string &section);
void clear()
- { bzero(regs, sizeof(regs)); }
+ { std::memset(regs, 0, sizeof(regs)); }
};
}
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index a350aa05f..773e7d10c 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -192,10 +192,10 @@ output decoder {{
}
const int AlphaFP::alphaToC99RoundingMode[] = {
- FE_TOWARDZERO, // Chopped
- FE_DOWNWARD, // Minus_Infinity
- FE_TONEAREST, // Normal
- FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
+ M5_FE_TOWARDZERO, // Chopped
+ M5_FE_DOWNWARD, // Minus_Infinity
+ M5_FE_TONEAREST, // Normal
+ M5_FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
};
const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
@@ -228,10 +228,10 @@ def template FloatingPointExecute {{
if (roundingMode == Normal) {
%(code)s;
} else {
- fesetround(getC99RoundingMode(
+ m5_fesetround(getC99RoundingMode(
xc->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR)));
%(code)s;
- fesetround(FE_TONEAREST);
+ m5_fesetround(M5_FE_TONEAREST);
}
#else
if (roundingMode != Normal && !warnedOnRounding) {
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index e9f126f12..714bca22a 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -213,7 +213,7 @@ TLB::flushAddr(Addr addr, uint8_t asn)
if (i == lookupTable.end())
return;
- while (i->first == vaddr.vpn()) {
+ while (i != lookupTable.end() && i->first == vaddr.vpn()) {
int index = i->second;
PTE *pte = &table[index];
assert(pte->valid);
@@ -225,10 +225,10 @@ TLB::flushAddr(Addr addr, uint8_t asn)
// invalidate this entry
pte->valid = false;
- lookupTable.erase(i);
+ lookupTable.erase(i++);
+ } else {
+ ++i;
}
-
- ++i;
}
}
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index bba63f407..4339003e0 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -154,6 +154,76 @@ def template ROrImmDecode {{
}
}};
+output header {{
+ union DoubleSingle
+ {
+ double d;
+ uint64_t ui;
+ uint32_t s[2];
+ DoubleSingle(double _d) : d(_d)
+ {}
+ DoubleSingle(uint64_t _ui) : ui(_ui)
+ {}
+ DoubleSingle(uint32_t _s0, uint32_t _s1)
+ {
+ s[0] = _s0;
+ s[1] = _s1;
+ }
+ };
+}};
+
+let {{
+ def filterDoubles(code):
+ assignRE = re.compile(r'\s*=(?!=)', re.MULTILINE)
+ for opName in ("Frd", "Frs1", "Frs2", "Frd_N"):
+ next_pos = 0
+ operandsREString = (r'''
+ (?<![\w\.]) # neg. lookbehind assertion: prevent partial matches
+ ((%s)(?:\.(\w+))?) # match: operand with optional '.' then suffix
+ (?![\w\.]) # neg. lookahead assertion: prevent partial matches
+ ''' % opName)
+ operandsRE = re.compile(operandsREString, re.MULTILINE|re.VERBOSE)
+ is_src = False
+ is_dest = False
+ extension = None
+ foundOne = False
+ while 1:
+ match = operandsRE.search(code, next_pos)
+ if not match:
+ break
+ foundOne = True
+ op = match.groups()
+ (op_full, op_base, op_ext) = op
+ is_dest_local = (assignRE.match(code, match.end()) != None)
+ is_dest = is_dest or is_dest_local
+ is_src = is_src or not is_dest_local
+ if extension and extension != op_ext:
+ raise Exception, "Inconsistent extensions in double filter."
+ extension = op_ext
+ next_pos = match.end()
+ if foundOne:
+ # Get rid of any unwanted extension
+ code = operandsRE.sub(op_base, code)
+ is_int = False
+ member = "d"
+ if extension in ("sb", "ub", "shw", "uhw", "sw", "uw", "sdw", "udw"):
+ is_int = True
+ member = "ui"
+ if is_src:
+ code = ("%s = DoubleSingle(%s_high, %s_low).%s;" % \
+ (opName, opName, opName, member)) + code
+ if is_dest:
+ code += '''
+ %s_low = DoubleSingle(%s).s[1];
+ %s_high = DoubleSingle(%s).s[0];''' % \
+ (opName, opName, opName, opName)
+ if is_int:
+ code = ("uint64_t %s;" % opName) + code
+ else:
+ code = ("double %s;" % opName) + code
+ return code
+}};
+
let {{
def splitOutImm(code):
matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>\d+)(?P<typeQual>\.\w+)?')
diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa
index 017f43780..5b0868132 100644
--- a/src/arch/sparc/isa/formats/basic.isa
+++ b/src/arch/sparc/isa/formats/basic.isa
@@ -97,6 +97,7 @@ def template BasicDecodeWithMnemonic {{
// The most basic instruction format... used only for a few misc. insts
def format BasicOperate(code, *flags) {{
+ code = filterDoubles(code)
iop = InstObjParams(name, Name, 'SparcStaticInst', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
@@ -108,38 +109,24 @@ def format FpBasic(code, *flags) {{
fp_code = """
Fsr |= bits(Fsr,4,0) << 5;
Fsr = insertBits(Fsr,4,0,0);
-#if defined(__sun) || defined (__OpenBSD__)
- fp_rnd newrnd = FP_RN;
+ int newrnd = M5_FE_TONEAREST;
switch (Fsr<31:30>) {
- case 0: newrnd = FP_RN; break;
- case 1: newrnd = FP_RZ; break;
- case 2: newrnd = FP_RP; break;
- case 3: newrnd = FP_RM; break;
+ case 0: newrnd = M5_FE_TONEAREST; break;
+ case 1: newrnd = M5_FE_TOWARDZERO; break;
+ case 2: newrnd = M5_FE_UPWARD; break;
+ case 3: newrnd = M5_FE_DOWNWARD; break;
}
- fp_rnd oldrnd = fpsetround(newrnd);
-#else
- int newrnd = FE_TONEAREST;
- switch (Fsr<31:30>) {
- case 0: newrnd = FE_TONEAREST; break;
- case 1: newrnd = FE_TOWARDZERO; break;
- case 2: newrnd = FE_UPWARD; break;
- case 3: newrnd = FE_DOWNWARD; break;
- }
- int oldrnd = fegetround();
- fesetround(newrnd);
-#endif
+ int oldrnd = m5_fegetround();
+ m5_fesetround(newrnd);
"""
fp_code += code
fp_code += """
-#if defined(__sun) || defined (__OpenBSD__)
- fpsetround(oldrnd);
-#else
- fesetround(oldrnd);
-#endif
+ m5_fesetround(oldrnd);
"""
+ fp_code = filterDoubles(fp_code)
iop = InstObjParams(name, Name, 'SparcStaticInst', fp_code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa
index 751262811..2f62c7bef 100644
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -71,6 +71,7 @@ let {{
}};
def format LoadAlt(code, asi, *opt_flags) {{
+ code = filterDoubles(code)
(header_output,
decoder_output,
exec_output,
@@ -79,6 +80,7 @@ def format LoadAlt(code, asi, *opt_flags) {{
}};
def format StoreAlt(code, asi, *opt_flags) {{
+ code = filterDoubles(code)
(header_output,
decoder_output,
exec_output,
@@ -87,6 +89,7 @@ def format StoreAlt(code, asi, *opt_flags) {{
}};
def format Load(code, *opt_flags) {{
+ code = filterDoubles(code)
(header_output,
decoder_output,
exec_output,
@@ -95,6 +98,7 @@ def format Load(code, *opt_flags) {{
}};
def format Store(code, *opt_flags) {{
+ code = filterDoubles(code)
(header_output,
decoder_output,
exec_output,
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa
index 499685a5c..e19016bd0 100644
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -317,6 +317,7 @@ let {{
}};
def format BlockLoad(code, asi, *opt_flags) {{
+ code = filterDoubles(code)
# We need to make sure to check the highest priority fault last.
# That way, if other faults have been detected, they'll be overwritten
# rather than the other way around.
@@ -329,6 +330,7 @@ def format BlockLoad(code, asi, *opt_flags) {{
}};
def format BlockStore(code, asi, *opt_flags) {{
+ code = filterDoubles(code)
# We need to make sure to check the highest priority fault last.
# That way, if other faults have been detected, they'll be overwritten
# rather than the other way around.
diff --git a/src/arch/sparc/isa/formats/mem/swap.isa b/src/arch/sparc/isa/formats/mem/swap.isa
index b71542a2b..f3d15670f 100644
--- a/src/arch/sparc/isa/formats/mem/swap.isa
+++ b/src/arch/sparc/isa/formats/mem/swap.isa
@@ -39,7 +39,7 @@ def template SwapExecute {{
Addr EA;
%(fp_enable_check)s;
%(op_decl)s;
- uint64_t mem_data;
+ uint64_t mem_data = 0;
%(op_rd)s;
%(ea_code)s;
diff --git a/src/arch/sparc/isa/formats/micro.isa b/src/arch/sparc/isa/formats/micro.isa
index 82d7fb4cb..da0f97d1b 100644
--- a/src/arch/sparc/isa/formats/micro.isa
+++ b/src/arch/sparc/isa/formats/micro.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright (c) 2006-2007 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -26,6 +26,33 @@
//
// Authors: Gabe Black
+//This delcares the initiateAcc function in memory operations
+def template MacroInitiateAcc {{
+ Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const
+ {
+ panic("Tried to execute a macroop directly!\n");
+ return NoFault;
+ }
+}};
+
+def template MacroCompleteAcc {{
+ Fault completeAcc(PacketPtr, %(CPU_exec_context)s *,
+ Trace::InstRecord *) const
+ {
+ panic("Tried to execute a macroop directly!\n");
+ return NoFault;
+ }
+}};
+
+//This template provides the execute functions for a store
+def template MacroExecute {{
+ Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
+ {
+ panic("Tried to execute a macroop directly!\n");
+ return NoFault;
+ }
+}};
+
output header {{
class SparcMacroInst : public SparcStaticInst
@@ -60,7 +87,9 @@ output header {{
return microOps[microPC];
}
- %(BasicExecPanic)s
+ %(MacroExecute)s
+ %(MacroInitiateAcc)s
+ %(MacroCompleteAcc)s
};
class SparcMicroInst : public SparcStaticInst
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index 05e9e8731..e9cd660b5 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -53,22 +53,14 @@ output decoder {{
#include "cpu/thread_context.hh" // for Jump::branchTarget()
#include "mem/packet.hh"
-#if defined(linux) || defined(__APPLE__)
-#include <fenv.h>
-#endif
+#include "base/fenv.hh"
#include <algorithm>
using namespace SparcISA;
}};
output exec {{
-#if defined(linux) || defined(__APPLE__)
-#include <fenv.h>
-#endif
-
-#if defined(__sun) || defined (__OpenBSD__)
-#include <ieeefp.h>
-#endif
+#include "base/fenv.hh"
#if FULL_SYSTEM
#include "sim/pseudo_inst.hh"
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index 038919bd1..58d616a7a 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -52,6 +52,16 @@ output header {{
{
return (regNum & (~1)) | ((regNum & 1) << 5);
}
+
+ static inline unsigned int dfprl(unsigned int regNum)
+ {
+ return dfpr(regNum) & (~0x1);
+ }
+
+ static inline unsigned int dfprh(unsigned int regNum)
+ {
+ return dfpr(regNum) | 0x1;
+ }
}};
def operands {{
@@ -79,21 +89,43 @@ def operands {{
# differently, they get different operands. The single precision versions
# have an s post pended to their name.
'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
- 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
+ #'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
+ 'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
+ 'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
# Each Frd_N refers to the Nth double precision register from Frd.
# Note that this adds twice N to the register number.
- 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
- 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
- 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
- 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
- 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
- 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
- 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
- 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
+ #'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
+ 'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
+ 'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
+ #'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
+ 'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10),
+ 'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10),
+ #'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
+ 'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10),
+ 'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10),
+ #'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
+ 'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10),
+ 'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10),
+ #'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
+ 'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10),
+ 'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10),
+ #'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
+ 'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10),
+ 'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10),
+ #'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
+ 'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10),
+ 'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10),
+ #'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
+ 'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10),
+ 'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10),
'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11),
- 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
+ #'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
+ 'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11),
+ 'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11),
'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12),
- 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
+ #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
+ 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12),
+ 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12),
'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
# Registers which are used explicitly in instructions
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index e4774ab54..d595664a0 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -39,6 +39,7 @@
#include "base/misc.hh"
#include "cpu/thread_context.hh"
#include "mem/page_table.hh"
+#include "sim/process_impl.hh"
#include "mem/translating_port.hh"
#include "sim/system.hh"
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index e6d1e4921..af7494598 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -95,6 +95,7 @@
#include "cpu/thread_context.hh"
#include "mem/page_table.hh"
#include "mem/translating_port.hh"
+#include "sim/process_impl.hh"
#include "sim/system.hh"
using namespace std;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 16:56:00 +0000