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-rw-r--r--src/arch/alpha/SConscript1
-rw-r--r--src/arch/alpha/ev5.cc2
-rw-r--r--src/arch/alpha/isa/fp.isa2
-rw-r--r--src/arch/alpha/isa/main.isa11
-rw-r--r--src/arch/alpha/isa_traits.hh8
-rw-r--r--src/arch/alpha/locked_mem.hh12
-rw-r--r--src/arch/alpha/miscregfile.cc161
-rw-r--r--src/arch/alpha/miscregfile.hh118
-rw-r--r--src/arch/alpha/regfile.hh56
-rw-r--r--src/arch/sparc/miscregfile.hh83
10 files changed, 332 insertions, 122 deletions
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index 3947ec23a..d9c9765a1 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -49,6 +49,7 @@ Import('env')
base_sources = Split('''
faults.cc
isa_traits.cc
+ miscregfile.cc
''')
# Full-system sources
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 59f9d2fb5..3d71fbda5 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -557,7 +557,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
void
AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
{
- for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) {
+ for (int i = 0; i < NumInternalProcRegs; ++i) {
dest->setMiscReg(i, src->readMiscReg(i));
}
}
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index 103f85775..3b5575f62 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -229,7 +229,7 @@ def template FloatingPointExecute {{
%(code)s;
} else {
fesetround(getC99RoundingMode(
- xc->readMiscReg(AlphaISA::Fpcr_DepTag)));
+ xc->readMiscReg(AlphaISA::MISCREG_FPCR)));
%(code)s;
fesetround(FE_TONEAREST);
}
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 06d3e8243..6e65cf9d3 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -184,9 +184,9 @@ def operands {{
'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
- 'Runiq': ('ControlReg', 'uq', 'AlphaISA::Uniq_DepTag', None, 1),
- 'FPCR': ('ControlReg', 'uq', 'AlphaISA::Fpcr_DepTag', None, 1),
- 'IntrFlag': ('ControlReg', 'uq', 'AlphaISA::Intr_Flag_DepTag', None, 1),
+ 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
+ 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
+ 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
# The next two are hacks for non-full-system call-pal emulation
'R0': ('IntReg', 'uq', '0', None, 1),
'R16': ('IntReg', 'uq', '16', None, 1),
@@ -216,11 +216,6 @@ output header {{
/// live here and not in the AlphaISA namespace.
enum DependenceTags {
FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
- Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
- Uniq_DepTag = AlphaISA::Uniq_DepTag,
- Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag,
- Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag,
- IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
};
/// Constructor.
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index a919a4a1f..3759b022b 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -50,13 +50,7 @@ namespace AlphaISA
// 0..31 are the integer regs 0..31
// 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
FP_Base_DepTag = 40,
- Ctrl_Base_DepTag = 72,
- Fpcr_DepTag = 72, // floating point control register
- Uniq_DepTag = 73,
- Lock_Flag_DepTag = 74,
- Lock_Addr_DepTag = 75,
- Intr_Flag_DepTag = 76,
- IPR_Base_DepTag = 77
+ Ctrl_Base_DepTag = 72
};
StaticInstPtr decodeInst(ExtMachInst);
diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index 368ea2895..52fe24173 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -37,7 +37,7 @@
* ISA-specific helper functions for locked memory accesses.
*/
-#include "arch/isa_traits.hh"
+#include "arch/alpha/miscregfile.hh"
#include "base/misc.hh"
#include "mem/request.hh"
@@ -48,8 +48,8 @@ template <class XC>
inline void
handleLockedRead(XC *xc, Request *req)
{
- xc->setMiscReg(Lock_Addr_DepTag, req->getPaddr() & ~0xf);
- xc->setMiscReg(Lock_Flag_DepTag, true);
+ xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
+ xc->setMiscReg(MISCREG_LOCKFLAG, true);
}
@@ -63,13 +63,13 @@ handleLockedWrite(XC *xc, Request *req)
req->setScResult(2);
} else {
// standard store conditional
- bool lock_flag = xc->readMiscReg(Lock_Flag_DepTag);
- Addr lock_addr = xc->readMiscReg(Lock_Addr_DepTag);
+ bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
+ Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
// Lock flag not set or addr mismatch in CPU;
// don't even bother sending to memory system
req->setScResult(0);
- xc->setMiscReg(Lock_Flag_DepTag, false);
+ xc->setMiscReg(MISCREG_LOCKFLAG, false);
// the rest of this code is not architectural;
// it's just a debugging aid to help detect
// livelock by warning on long sequences of failed
diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc
new file mode 100644
index 000000000..4cf57a690
--- /dev/null
+++ b/src/arch/alpha/miscregfile.cc
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ * Gabe Black
+ * Kevin Lim
+ */
+
+#include "arch/alpha/miscregfile.hh"
+#include "base/misc.hh"
+
+namespace AlphaISA
+{
+
+ void
+ MiscRegFile::serialize(std::ostream &os)
+ {
+ SERIALIZE_SCALAR(fpcr);
+ SERIALIZE_SCALAR(uniq);
+ SERIALIZE_SCALAR(lock_flag);
+ SERIALIZE_SCALAR(lock_addr);
+#if FULL_SYSTEM
+ SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
+#endif
+ }
+
+ void
+ MiscRegFile::unserialize(Checkpoint *cp, const std::string &section)
+ {
+ UNSERIALIZE_SCALAR(fpcr);
+ UNSERIALIZE_SCALAR(uniq);
+ UNSERIALIZE_SCALAR(lock_flag);
+ UNSERIALIZE_SCALAR(lock_addr);
+#if FULL_SYSTEM
+ UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
+#endif
+ }
+
+ MiscReg
+ MiscRegFile::readReg(int misc_reg)
+ {
+ switch(misc_reg) {
+ case MISCREG_FPCR:
+ return fpcr;
+ case MISCREG_UNIQ:
+ return uniq;
+ case MISCREG_LOCKFLAG:
+ return lock_flag;
+ case MISCREG_LOCKADDR:
+ return lock_addr;
+ case MISCREG_INTR:
+ return intr_flag;
+#if FULL_SYSTEM
+ default:
+ assert(misc_reg < NumInternalProcRegs);
+ return ipr[misc_reg];
+#else
+ default:
+ panic("Attempt to read an invalid misc register!");
+ return 0;
+#endif
+ }
+ }
+
+ MiscReg
+ MiscRegFile::readRegWithEffect(int misc_reg, ThreadContext *tc)
+ {
+#if FULL_SYSTEM
+ return readIpr(misc_reg, tc);
+#else
+ panic("No faulting misc regs in SE mode!");
+ return 0;
+#endif
+ }
+
+ void
+ MiscRegFile::setReg(int misc_reg, const MiscReg &val)
+ {
+ switch(misc_reg) {
+ case MISCREG_FPCR:
+ fpcr = val;
+ return;
+ case MISCREG_UNIQ:
+ uniq = val;
+ return;
+ case MISCREG_LOCKFLAG:
+ lock_flag = val;
+ return;
+ case MISCREG_LOCKADDR:
+ lock_addr = val;
+ return;
+ case MISCREG_INTR:
+ intr_flag = val;
+ return;
+#if FULL_SYSTEM
+ default:
+ assert(misc_reg < NumInternalProcRegs);
+ ipr[misc_reg] = val;
+ return;
+#else
+ default:
+ panic("Attempt to write to an invalid misc register!");
+#endif
+ }
+ }
+
+ void
+ MiscRegFile::setRegWithEffect(int misc_reg, const MiscReg &val,
+ ThreadContext *tc)
+ {
+#if FULL_SYSTEM
+ switch(misc_reg) {
+ case MISCREG_FPCR:
+ fpcr = val;
+ return;
+ case MISCREG_UNIQ:
+ uniq = val;
+ return;
+ case MISCREG_LOCKFLAG:
+ lock_flag = val;
+ return;
+ case MISCREG_LOCKADDR:
+ lock_addr = val;
+ return;
+ case MISCREG_INTR:
+ intr_flag = val;
+ return;
+ default:
+ return setIpr(misc_reg, val, tc);
+ }
+#else
+ //panic("No registers with side effects in SE mode!");
+ return;
+#endif
+ }
+
+}
diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh
new file mode 100644
index 000000000..85cb054bb
--- /dev/null
+++ b/src/arch/alpha/miscregfile.hh
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ * Gabe Black
+ */
+
+#ifndef __ARCH_ALPHA_MISCREGFILE_HH__
+#define __ARCH_ALPHA_MISCREGFILE_HH__
+
+#include "arch/alpha/ipr.hh"
+#include "arch/alpha/types.hh"
+#include "config/full_system.hh"
+#include "sim/host.hh"
+#include "sim/serialize.hh"
+
+#include <iostream>
+
+class Checkpoint;
+class ThreadContext;
+
+namespace AlphaISA
+{
+ enum MiscRegIndex
+ {
+ MISCREG_FPCR = NumInternalProcRegs,
+ MISCREG_UNIQ,
+ MISCREG_LOCKFLAG,
+ MISCREG_LOCKADDR,
+ MISCREG_INTR
+ };
+
+ class MiscRegFile {
+ protected:
+ uint64_t fpcr; // floating point condition codes
+ uint64_t uniq; // process-unique register
+ bool lock_flag; // lock flag for LL/SC
+ Addr lock_addr; // lock address for LL/SC
+ int intr_flag;
+
+ public:
+ MiscRegFile()
+ {
+#if FULL_SYSTEM
+ initializeIprTable();
+#endif
+ }
+
+ MiscReg readReg(int misc_reg);
+
+ MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc);
+
+ //These functions should be removed once the simplescalar cpu model
+ //has been replaced.
+ int getInstAsid();
+ int getDataAsid();
+
+ void setReg(int misc_reg, const MiscReg &val);
+
+ void setRegWithEffect(int misc_reg, const MiscReg &val,
+ ThreadContext *tc);
+
+ void clear()
+ {
+ fpcr = uniq = 0;
+ lock_flag = 0;
+ lock_addr = 0;
+ intr_flag = 0;
+ }
+
+ void serialize(std::ostream &os);
+
+ void unserialize(Checkpoint *cp, const std::string &section);
+#if FULL_SYSTEM
+ protected:
+ typedef uint64_t InternalProcReg;
+
+ InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
+
+ private:
+ InternalProcReg readIpr(int idx, ThreadContext *tc);
+
+ void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
+#endif
+ friend class RegFile;
+ };
+
+#if FULL_SYSTEM
+ void copyIprs(ThreadContext *src, ThreadContext *dest);
+#endif
+
+}
+
+#endif
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index e806adbcb..af28f6c6f 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -33,6 +33,7 @@
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/ipr.hh"
+#include "arch/alpha/miscregfile.hh"
#include "arch/alpha/types.hh"
#include "sim/faults.hh"
@@ -104,61 +105,6 @@ namespace AlphaISA
{ bzero(d, sizeof(d)); }
};
- class MiscRegFile {
- protected:
- uint64_t fpcr; // floating point condition codes
- uint64_t uniq; // process-unique register
- bool lock_flag; // lock flag for LL/SC
- Addr lock_addr; // lock address for LL/SC
- int intr_flag;
-
- public:
- MiscRegFile()
- {
-#if FULL_SYSTEM
- initializeIprTable();
-#endif
- }
-
- MiscReg readReg(int misc_reg);
-
- MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc);
-
- //These functions should be removed once the simplescalar cpu model
- //has been replaced.
- int getInstAsid();
- int getDataAsid();
-
- void setReg(int misc_reg, const MiscReg &val);
-
- void setRegWithEffect(int misc_reg, const MiscReg &val,
- ThreadContext *tc);
-
- void clear()
- {
- fpcr = uniq = 0;
- lock_flag = 0;
- lock_addr = 0;
- intr_flag = 0;
- }
-
- void serialize(std::ostream &os);
-
- void unserialize(Checkpoint *cp, const std::string &section);
-#if FULL_SYSTEM
- protected:
- typedef uint64_t InternalProcReg;
-
- InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
-
- private:
- InternalProcReg readIpr(int idx, ThreadContext *tc);
-
- void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
-#endif
- friend class RegFile;
- };
-
class RegFile {
protected:
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index 0e424dbd2..6d624787d 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -46,59 +46,54 @@ namespace SparcISA
//These functions map register indices to names
std::string getMiscRegName(RegIndex);
- const int AsrStart = 0;
- const int PrStart = 32;
- const int HprStart = 64;
- const int MiscStart = 96;
-
enum MiscRegIndex
{
/** Ancillary State Registers */
- MISCREG_Y = AsrStart + 0,
- MISCREG_CCR = AsrStart + 2,
- MISCREG_ASI = AsrStart + 3,
- MISCREG_TICK = AsrStart + 4,
- MISCREG_FPRS = AsrStart + 6,
- MISCREG_PCR = AsrStart + 16,
- MISCREG_PIC = AsrStart + 17,
- MISCREG_GSR = AsrStart + 19,
- MISCREG_SOFTINT_SET = AsrStart + 20,
- MISCREG_SOFTINT_CLR = AsrStart + 21,
- MISCREG_SOFTINT = AsrStart + 22,
- MISCREG_TICK_CMPR = AsrStart + 23,
- MISCREG_STICK = AsrStart + 24,
- MISCREG_STICK_CMPR = AsrStart + 25,
+ MISCREG_Y,
+ MISCREG_CCR,
+ MISCREG_ASI,
+ MISCREG_TICK,
+ MISCREG_FPRS,
+ MISCREG_PCR,
+ MISCREG_PIC,
+ MISCREG_GSR,
+ MISCREG_SOFTINT_SET,
+ MISCREG_SOFTINT_CLR,
+ MISCREG_SOFTINT,
+ MISCREG_TICK_CMPR,
+ MISCREG_STICK,
+ MISCREG_STICK_CMPR,
/** Privilged Registers */
- MISCREG_TPC = PrStart + 0,
- MISCREG_TNPC = PrStart + 1,
- MISCREG_TSTATE = PrStart + 2,
- MISCREG_TT = PrStart + 3,
- MISCREG_PRIVTICK = PrStart + 4,
- MISCREG_TBA = PrStart + 5,
- MISCREG_PSTATE = PrStart + 6,
- MISCREG_TL = PrStart + 7,
- MISCREG_PIL = PrStart + 8,
- MISCREG_CWP = PrStart + 9,
- MISCREG_CANSAVE = PrStart + 10,
- MISCREG_CANRESTORE = PrStart + 11,
- MISCREG_CLEANWIN = PrStart + 12,
- MISCREG_OTHERWIN = PrStart + 13,
- MISCREG_WSTATE = PrStart + 14,
- MISCREG_GL = PrStart + 16,
+ MISCREG_TPC,
+ MISCREG_TNPC,
+ MISCREG_TSTATE,
+ MISCREG_TT,
+ MISCREG_PRIVTICK,
+ MISCREG_TBA,
+ MISCREG_PSTATE,
+ MISCREG_TL,
+ MISCREG_PIL,
+ MISCREG_CWP,
+ MISCREG_CANSAVE,
+ MISCREG_CANRESTORE,
+ MISCREG_CLEANWIN,
+ MISCREG_OTHERWIN,
+ MISCREG_WSTATE,
+ MISCREG_GL,
/** Hyper privileged registers */
- MISCREG_HPSTATE = HprStart + 0,
- MISCREG_HTSTATE = HprStart + 1,
- MISCREG_HINTP = HprStart + 3,
- MISCREG_HTBA = HprStart + 5,
- MISCREG_HVER = HprStart + 6,
- MISCREG_STRAND_STS_REG = HprStart + 16,
- MISCREG_HSTICK_CMPR = HprStart + 31,
+ MISCREG_HPSTATE,
+ MISCREG_HTSTATE,
+ MISCREG_HINTP,
+ MISCREG_HTBA,
+ MISCREG_HVER,
+ MISCREG_STRAND_STS_REG,
+ MISCREG_HSTICK_CMPR,
/** Floating Point Status Register */
- MISCREG_FSR = MiscStart + 0
-
+ MISCREG_FSR,
+ NumMiscRegs
};
// The control registers, broken out into fields
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 11:32:38 +0000