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-rw-r--r--src/arch/arm/isa/insts/m5ops.isa7
-rw-r--r--src/arch/mips/faults.cc4
-rw-r--r--src/arch/mips/faults.hh14
-rw-r--r--src/arch/mips/isa/decoder.isa2
-rw-r--r--src/arch/mips/linux/process.cc2
-rw-r--r--src/arch/mips/registers.hh2
-rw-r--r--src/arch/mips/tlb.cc14
-rw-r--r--src/arch/x86/isa/insts/general_purpose/input_output/general_io.py8
-rw-r--r--src/arch/x86/isa/insts/general_purpose/input_output/string_io.py8
9 files changed, 38 insertions, 23 deletions
diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index a157b414c..da2e10886 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -190,12 +190,15 @@ let {{
exec_output += PredOpExecute.subst(loadsymbolIop)
initparamCode = '''
- Rt = PseudoInst::initParam(xc->tcBase());
+ uint64_t ip_val = PseudoInst::initParam(xc->tcBase());
+ R0 = bits(ip_val, 31, 0);
+ R1 = bits(ip_val, 63, 32);
'''
initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
{ "code": initparamCode,
- "predicate_test": predicateTest })
+ "predicate_test": predicateTest },
+ ["IsNonSpeculative"])
header_output += BasicDeclare.subst(initparamIop)
decoder_output += BasicConstructor.subst(initparamIop)
exec_output += PredOpExecute.subst(initparamIop)
diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 524efa178..3076e0afe 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -29,6 +29,8 @@
* Authors: Gabe Black
* Korey Sewell
* Jaidev Patwardhan
+ * Zhengxing Li
+ * Deyuan Guo
*/
#include "arch/mips/faults.hh"
@@ -118,7 +120,7 @@ MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
DPRINTF(MipsPRA, "PC: %s\n", pc);
bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
tc->setMiscRegNoEffect(MISCREG_EPC,
- pc.pc() - delay_slot ? sizeof(MachInst) : 0);
+ pc.pc() - (delay_slot ? sizeof(MachInst) : 0));
// Set Cause_EXCCODE field
CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index bce828ec1..b90c38e99 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -29,6 +29,8 @@
* Authors: Gabe Black
* Korey Sewell
* Jaidev Patwardhan
+ * Zhengxing Li
+ * Deyuan Guo
*/
#ifndef __MIPS_FAULTS_HH__
@@ -88,7 +90,7 @@ class MipsFaultBase : public FaultBase
virtual FaultVect base(ThreadContext *tc) const
{
StatusReg status = tc->readMiscReg(MISCREG_STATUS);
- if (status.bev)
+ if (!status.bev)
return tc->readMiscReg(MISCREG_EBASE);
else
return 0xbfc00200;
@@ -167,7 +169,7 @@ class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
if (FullSystem) {
CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
cause.ce = coProcID;
- tc->setMiscReg(MISCREG_CAUSE, cause);
+ tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
}
}
};
@@ -179,7 +181,8 @@ class InterruptFault : public MipsFault<InterruptFault>
offset(ThreadContext *tc) const
{
CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
- return cause.iv ? 0x200 : 0x000;
+ // offset 0x200 for release 2, 0x180 for release 1.
+ return cause.iv ? 0x200 : 0x180;
}
};
@@ -251,9 +254,10 @@ class TlbFault : public AddressFault<T>
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
if (FullSystem) {
- DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
- tc->pcState(this->vect(tc));
+ DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name());
+ Addr vect = this->vect(tc);
setTlbExceptionState(tc, this->code());
+ tc->pcState(vect);
} else {
AddressFault<T>::invoke(tc, inst);
}
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 193f050de..034133f96 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -1253,7 +1253,7 @@ decode OPCODE_HI default Unknown::unknown() {
//When rs=L1
//Note: "1. Format type L is legal only if 64-bit
//floating point operations are enabled."
- 0x5: decode FUNCTION_HI {
+ 0x5: decode FUNCTION {
format FloatConvertOp {
0x20: cvt_s_l({{ val = Fs_ud; }}, ToSingle);
0x21: cvt_d_l({{ val = Fs_ud; }}, ToDouble);
diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc
index 156d4ea05..0982e05cb 100644
--- a/src/arch/mips/linux/process.cc
+++ b/src/arch/mips/linux/process.cc
@@ -55,7 +55,7 @@ unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
strcpy(name->sysname, "Linux");
strcpy(name->nodename,"m5.eecs.umich.edu");
- strcpy(name->release, "2.4.20");
+ strcpy(name->release, "2.6.35");
strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
strcpy(name->machine, "mips");
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index dce7858bf..d3cf1650d 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -55,7 +55,7 @@ const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
const uint32_t MIPS32_QNAN = 0x7fbfffff;
-const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff);
+const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff);
enum FPControlRegNums {
FLOATREG_FIR = NumFloatArchRegs,
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 057fb5e76..d28ef8231 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -29,6 +29,8 @@
* Authors: Nathan Binkert
* Steve Reinhardt
* Jaidev Patwardhan
+ * Zhengxing Li
+ * Deyuan Guo
*/
#include <string>
@@ -310,18 +312,6 @@ Fault
TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
{
if (!FullSystem) {
- //@TODO: This should actually use TLB instead of going directly
- // to the page table in syscall mode.
- /**
- * Check for alignment faults
- */
- if (req->getVaddr() & (req->getSize() - 1)) {
- DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
- req->getSize());
- return new AddressErrorFault(req->getVaddr(), write);
- }
-
-
Process * p = tc->getProcessPtr();
Fault fault = p->pTable->translate(req);
diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
index c034f8a48..0465b3447 100644
--- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
@@ -42,26 +42,34 @@ microcode = '''
def macroop IN_R_I {
.adjust_imm trimImm(8)
limm t1, imm, dataSize=asz
+ mfence
ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \
nonSpec=True
+ mfence
};
def macroop IN_R_R {
zexti t2, regm, 15, dataSize=8
+ mfence
ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
nonSpec=True
+ mfence
};
def macroop OUT_I_R {
.adjust_imm trimImm(8)
limm t1, imm, dataSize=8
+ mfence
st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \
nonSpec=True
+ mfence
};
def macroop OUT_R_R {
zexti t2, reg, 15, dataSize=8
+ mfence
st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
nonSpec=True
+ mfence
};
'''
diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
index 3c90ee7e7..044e57edc 100644
--- a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
@@ -45,9 +45,11 @@ def macroop INS_M_R {
zexti t2, reg, 15, dataSize=8
+ mfence
ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
nonSpec=True
st t6, es, [1, t0, rdi]
+ mfence
add rdi, rdi, t3, dataSize=asz
};
@@ -63,6 +65,7 @@ def macroop INS_E_M_R {
zexti t2, reg, 15, dataSize=8
+ mfence
topOfLoop:
ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
nonSpec=True
@@ -72,6 +75,7 @@ topOfLoop:
add rdi, rdi, t3, dataSize=asz
br label("topOfLoop"), flags=(nCEZF,)
end:
+ mfence
fault "NoFault"
};
@@ -84,9 +88,11 @@ def macroop OUTS_R_M {
zexti t2, reg, 15, dataSize=8
+ mfence
ld t6, ds, [1, t0, rsi]
st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
nonSpec=True
+ mfence
add rsi, rsi, t3, dataSize=asz
};
@@ -102,6 +108,7 @@ def macroop OUTS_E_R_M {
zexti t2, reg, 15, dataSize=8
+ mfence
topOfLoop:
ld t6, ds, [1, t0, rsi]
st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
@@ -111,6 +118,7 @@ topOfLoop:
add rsi, rsi, t3, dataSize=asz
br label("topOfLoop"), flags=(nCEZF,)
end:
+ mfence
fault "NoFault"
};
'''
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 06:08:41 +0000