diff options
Diffstat (limited to 'src/arch')
29 files changed, 379 insertions, 13 deletions
diff --git a/src/arch/SConscript b/src/arch/SConscript index ea940560d..e30069c04 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -1,5 +1,17 @@ # -*- mode:python -*- +# Copyright (c) 2016 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2006 The Regents of The University of Michigan # All rights reserved. # @@ -202,6 +214,7 @@ env.Append(BUILDERS = {'ScanISA' : DebugFlag('IntRegs') DebugFlag('FloatRegs') +DebugFlag('VecRegs') DebugFlag('CCRegs') DebugFlag('MiscRegs') CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'CCRegs', 'MiscRegs' ]) diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh index 80d8ab149..36e708450 100644 --- a/src/arch/alpha/isa.hh +++ b/src/arch/alpha/isa.hh @@ -110,6 +110,18 @@ namespace AlphaISA return reg; } + int + flattenVecIndex(int reg) const + { + return reg; + } + + int + flattenVecElemIndex(int reg) const + { + return reg; + } + // dummy int flattenCCIndex(int reg) const diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh index 03bbd8aaf..151ea7d7c 100644 --- a/src/arch/alpha/registers.hh +++ b/src/arch/alpha/registers.hh @@ -34,6 +34,7 @@ #include "arch/alpha/generated/max_inst_regs.hh" #include "arch/alpha/ipr.hh" #include "arch/generic/types.hh" +#include "arch/generic/vec_reg.hh" #include "base/types.hh" namespace AlphaISA { @@ -56,6 +57,15 @@ typedef uint64_t MiscReg; // dummy typedef since we don't have CC regs typedef uint8_t CCReg; +// dummy typedefs since we don't have vector regs +constexpr unsigned NumVecElemPerVecReg = 2; +using VecElem = uint32_t; +using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; +using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; +using VecRegContainer = VecReg::Container; +// This has to be one to prevent warnings that are treated as errors +constexpr unsigned NumVecRegs = 1; + union AnyReg { IntReg intreg; diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py index 73ef4a09d..7956570bd 100644 --- a/src/arch/arm/ArmISA.py +++ b/src/arch/arm/ArmISA.py @@ -41,6 +41,7 @@ from m5.proxy import * from m5.SimObject import SimObject from ArmPMU import ArmPMU +from ISACommon import VecRegRenameMode # Enum for DecoderFlavour class DecoderFlavour(Enum): vals = ['Generic'] @@ -86,6 +87,10 @@ class ArmISA(SimObject): id_aa64afr1_el1 = Param.UInt64(0x0000000000000000, "AArch64 Auxiliary Feature Register 1") + # Initial vector register rename mode + vecRegRenameMode = Param.VecRegRenameMode('Full', + "Initial rename mode for vecregs") + # 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006, "AArch64 Debug Feature Register 0") diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index 99d1b817d..8501715d5 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -331,6 +331,12 @@ ArmStaticInst::printFloatReg(std::ostream &os, RegIndex reg_idx) const } void +ArmStaticInst::printVecReg(std::ostream &os, RegIndex reg_idx) const +{ + ccprintf(os, "v%d", reg_idx); +} + +void ArmStaticInst::printCCReg(std::ostream &os, RegIndex reg_idx) const { ccprintf(os, "cc_%s", ArmISA::ccRegName[reg_idx]); diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh index 19af99a0f..486d30fe4 100644 --- a/src/arch/arm/insts/static_inst.hh +++ b/src/arch/arm/insts/static_inst.hh @@ -157,6 +157,7 @@ class ArmStaticInst : public StaticInst /// dependence tag number (FP or int). void printIntReg(std::ostream &os, RegIndex reg_idx) const; void printFloatReg(std::ostream &os, RegIndex reg_idx) const; + void printVecReg(std::ostream &os, RegIndex reg_idx) const; void printCCReg(std::ostream &os, RegIndex reg_idx) const; void printMiscReg(std::ostream &os, RegIndex reg_idx) const; void printMnemonic(std::ostream &os, diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index c54d7746d..a490e5fb7 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -209,6 +209,7 @@ ISA::ISA(Params *p) : SimObject(p), system(NULL), _decoderFlavour(p->decoderFlavour), + _vecRegRenameMode(p->vecRegRenameMode), pmu(p->pmu), lookUpMiscReg(NUM_MISCREGS, {0,0}) { diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 8de90dc93..e96de7922 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -48,7 +48,9 @@ #include "arch/arm/system.hh" #include "arch/arm/tlb.hh" #include "arch/arm/types.hh" +#include "arch/generic/traits.hh" #include "debug/Checkpoint.hh" +#include "enums/VecRegRenameMode.hh" #include "sim/sim_object.hh" #include "enums/DecoderFlavour.hh" @@ -68,6 +70,7 @@ namespace ArmISA // Micro Architecture const Enums::DecoderFlavour _decoderFlavour; + const Enums::VecRegRenameMode _vecRegRenameMode; /** Dummy device for to handle non-existing ISA devices */ DummyISADevice dummyDevice; @@ -185,6 +188,10 @@ namespace ArmISA return RegId(IntRegClass, flattenIntIndex(regId.index())); case FloatRegClass: return RegId(FloatRegClass, flattenFloatIndex(regId.index())); + case VecRegClass: + return RegId(VecRegClass, flattenVecIndex(regId.index())); + case VecElemClass: + return RegId(VecElemClass, flattenVecElemIndex(regId.index())); case CCRegClass: return RegId(CCRegClass, flattenCCIndex(regId.index())); case MiscRegClass: @@ -233,6 +240,20 @@ namespace ArmISA } int + flattenVecIndex(int reg) const + { + assert(reg >= 0); + return reg; + } + + int + flattenVecElemIndex(int reg) const + { + assert(reg >= 0); + return reg; + } + + int flattenCCIndex(int reg) const { assert(reg >= 0); @@ -406,6 +427,12 @@ namespace ArmISA Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; } + Enums::VecRegRenameMode + vecRegRenameMode() const + { + return _vecRegRenameMode; + } + /// Explicitly import the otherwise hidden startup using SimObject::startup; @@ -417,4 +444,17 @@ namespace ArmISA }; } +template<> +struct initRenameMode<ArmISA::ISA> +{ + static Enums::VecRegRenameMode mode(const ArmISA::ISA* isa) + { + return isa->vecRegRenameMode(); + } + static bool equals(const ArmISA::ISA* isa1, const ArmISA::ISA* isa2) + { + return mode(isa1) == mode(isa2); + } +}; + #endif diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc index fcb13fb2a..395232e00 100644 --- a/src/arch/arm/nativetrace.cc +++ b/src/arch/arm/nativetrace.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2011, 2014 ARM Limited + * Copyright (c) 2010-2011, 2014, 2016 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -125,10 +125,10 @@ Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc) newState[STATE_CPSR] = cpsr; changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]); - for (int i = 0; i < NumFloatV7ArchRegs; i += 2) { - newState[STATE_F0 + (i >> 1)] = - static_cast<uint64_t>(tc->readFloatRegBits(i + 1)) << 32 | - tc->readFloatRegBits(i); + for (int i = 0; i < NumVecV7ArchRegs; i++) { + auto vec(tc->readVecReg(RegId(VecRegClass,i)).as<uint64_t, 2>()); + newState[STATE_F0 + 2*i] = vec[0]; + newState[STATE_F0 + 2*i + 1] = vec[1]; } newState[STATE_FPSCR] = tc->readMiscRegNoEffect(MISCREG_FPSCR) | tc->readCCReg(CCREG_FP); diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh index 2e1ad1881..0a617e4dc 100644 --- a/src/arch/arm/registers.hh +++ b/src/arch/arm/registers.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2011, 2014 ARM Limited + * Copyright (c) 2010-2011, 2014, 2016 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -43,10 +43,11 @@ #ifndef __ARCH_ARM_REGISTERS_HH__ #define __ARCH_ARM_REGISTERS_HH__ +#include "arch/arm/ccregs.hh" #include "arch/arm/generated/max_inst_regs.hh" #include "arch/arm/intregs.hh" -#include "arch/arm/ccregs.hh" #include "arch/arm/miscregs.hh" +#include "arch/generic/vec_reg.hh" namespace ArmISA { @@ -64,6 +65,13 @@ typedef uint64_t IntReg; typedef uint32_t FloatRegBits; typedef float FloatReg; +// Number of VecElem per Vector Register, computed based on the vector length +constexpr unsigned NumVecElemPerVecReg = 4; +using VecElem = uint32_t; +using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; +using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; +using VecRegContainer = VecReg::Container; + // cop-0/cop-1 system control register typedef uint64_t MiscReg; @@ -76,15 +84,19 @@ const int NumIntArchRegs = NUM_ARCH_INTREGS; const int NumFloatV7ArchRegs = 64; const int NumFloatV8ArchRegs = 128; const int NumFloatSpecialRegs = 32; +const int NumVecV7ArchRegs = 64; +const int NumVecV8ArchRegs = 32; +const int NumVecSpecialRegs = 8; const int NumIntRegs = NUM_INTREGS; const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; +const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs; const int NumCCRegs = NUM_CCREGS; const int NumMiscRegs = NUM_MISCREGS; #define ISA_HAS_CC_REGS -const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; +const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs + NumMiscRegs; // semantically meaningful register indices const int ReturnValueReg = 0; diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc index eefe62b42..d934d53d3 100644 --- a/src/arch/arm/remote_gdb.cc +++ b/src/arch/arm/remote_gdb.cc @@ -1,7 +1,7 @@ /* * Copyright 2015 LabWare * Copyright 2014 Google Inc. - * Copyright (c) 2010, 2013 ARM Limited + * Copyright (c) 2010, 2013, 2016 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -212,6 +212,10 @@ RemoteGDB::AArch64GdbRegCache::getRegs(ThreadContext *context) r.v[i + 2] = context->readFloatRegBits(i + 0); r.v[i + 3] = context->readFloatRegBits(i + 1); } + + for (int i = 0; i < 32; i ++) { + r.vec[i] = context->readVecReg(RegId(VecRegClass,i)); + } } void @@ -234,6 +238,10 @@ RemoteGDB::AArch64GdbRegCache::setRegs(ThreadContext *context) const context->setFloatRegBits(i + 0, r.v[i + 2]); context->setFloatRegBits(i + 1, r.v[i + 3]); } + + for (int i = 0; i < 32; i ++) { + context->setVecReg(RegId(VecRegClass, i), r.vec[i]); + } } void diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh index acd6f32d2..328fbadb3 100644 --- a/src/arch/arm/remote_gdb.hh +++ b/src/arch/arm/remote_gdb.hh @@ -1,7 +1,7 @@ /* * Copyright 2015 LabWare * Copyright 2014 Google, Inc. - * Copyright (c) 2013 ARM Limited + * Copyright (c) 2013, 2016 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -51,6 +51,7 @@ #include <algorithm> #include "arch/arm/utility.hh" +#include "arch/generic/vec_reg.hh" #include "base/remote_gdb.hh" class System; @@ -96,6 +97,7 @@ class RemoteGDB : public BaseRemoteGDB uint64_t pc; uint64_t cpsr; uint32_t v[32*4]; + ArmISA::VecRegContainer vec[32]; } r; public: char *data() const { return (char *)&r; } diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 1437801a2..a58ca8111 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -154,6 +154,9 @@ copyRegs(ThreadContext *src, ThreadContext *dest) for (int i = 0; i < NumFloatRegs; i++) dest->setFloatRegFlat(i, src->readFloatRegFlat(i)); + for (int i = 0; i < NumVecRegs; i++) + dest->setVecRegFlat(i, src->readVecRegFlat(i)); + for (int i = 0; i < NumCCRegs; i++) dest->setCCReg(i, src->readCCReg(i)); diff --git a/src/arch/generic/ISACommon.py b/src/arch/generic/ISACommon.py new file mode 100644 index 000000000..7777dc27e --- /dev/null +++ b/src/arch/generic/ISACommon.py @@ -0,0 +1,50 @@ +# Copyright (c) 2016 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Rekai Gonzalez + +from m5.params import * +from m5.proxy import * +from m5.SimObject import SimObject + +class VecRegRenameMode(Enum): + '''Enum for Rename Mode in rename map + Elem: Each native-elem in a vector register is renamed independently. + Full: Vectors are renamed as one unit.''' + + vals = ['Full', 'Elem'] + + +__all__ = ['VecRegRenameMode'] diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript index c87ad671f..7123eaf4a 100644 --- a/src/arch/generic/SConscript +++ b/src/arch/generic/SConscript @@ -1,3 +1,15 @@ +# Copyright (c) 2016 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2012 Google # All rights reserved. # @@ -36,6 +48,7 @@ Source('mmapped_ipr.cc') Source('tlb.cc') SimObject('BaseTLB.py') +SimObject('ISACommon.py') DebugFlag('TLB') Source('pseudo_inst.cc') diff --git a/src/arch/generic/traits.hh b/src/arch/generic/traits.hh new file mode 100644 index 000000000..3dc6b30ee --- /dev/null +++ b/src/arch/generic/traits.hh @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2016 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Rekai Gonzalez + */ + +/* Auxiliary structs for architecture traits. */ + +#ifndef __ARCH_COMMON_TRAITS_HH__ +#define __ARCH_COMMON_TRAITS_HH__ + +#include "enums/VecRegRenameMode.hh" + +/** Helper structure to get the vector register mode for a given ISA. + * This way we implement a default 'full' mode, and only those ISA that care + * have to actually specialise the template to forward the call to the + * appropriate member of the ISA. + */ +template <typename ISA> +struct initRenameMode +{ + static Enums::VecRegRenameMode mode(const ISA*) { return Enums::Full; } + /** + * Compare the initial rename mode of two instances of the ISA. + * Result is true by definition, as the default mode is Full. + * */ + static bool equals(const ISA*, const ISA*) { return true; } +}; + +#endif /* __ARCH_COMMON_TRAITS_HH__ */ diff --git a/src/arch/generic/types.hh b/src/arch/generic/types.hh index bb6eafd66..353112913 100644 --- a/src/arch/generic/types.hh +++ b/src/arch/generic/types.hh @@ -40,6 +40,9 @@ // Logical register index type. typedef uint16_t RegIndex; +/** Logical vector register elem index type. */ +using ElemIndex = uint16_t; + namespace GenericISA { diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 610197e38..759b50c0d 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1,4 +1,4 @@ -# Copyright (c) 2014 ARM Limited +# Copyright (c) 2014, 2016 ARM Limited # All rights reserved # # The license below extends only to copyright in the software and shall @@ -865,8 +865,8 @@ class OperandList(object): op_desc = self.find_base(op_base) if op_desc: if op_desc.ext != op_ext: - error('Inconsistent extensions for operand %s' % \ - op_base) + error ('Inconsistent extensions for operand %s' % \ + op_base) op_desc.is_src = op_desc.is_src or is_src op_desc.is_dest = op_desc.is_dest or is_dest else: diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh index c751cb168..c38b7cec0 100644 --- a/src/arch/mips/isa.hh +++ b/src/arch/mips/isa.hh @@ -180,6 +180,18 @@ namespace MipsISA return reg; } + int + flattenVecIndex(int reg) const + { + return reg; + } + + int + flattenVecElemIndex(int reg) const + { + return reg; + } + // dummy int flattenCCIndex(int reg) const diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh index c7cdb6522..f5dd325cd 100644 --- a/src/arch/mips/registers.hh +++ b/src/arch/mips/registers.hh @@ -32,6 +32,7 @@ #ifndef __ARCH_MIPS_REGISTERS_HH__ #define __ARCH_MIPS_REGISTERS_HH__ +#include "arch/generic/vec_reg.hh" #include "arch/mips/generated/max_inst_regs.hh" #include "base/misc.hh" #include "base/types.hh" @@ -289,6 +290,15 @@ typedef uint64_t MiscReg; // dummy typedef since we don't have CC regs typedef uint8_t CCReg; +// dummy typedefs since we don't have vector regs +constexpr unsigned NumVecElemPerVecReg = 2; +using VecElem = uint32_t; +using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; +using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; +using VecRegContainer = VecReg::Container; +// This has to be one to prevent warnings that are treated as errors +constexpr unsigned NumVecRegs = 1; + typedef union { IntReg intreg; FloatReg fpreg; diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh index 6d1ecf1c5..3d27d95a2 100644 --- a/src/arch/null/registers.hh +++ b/src/arch/null/registers.hh @@ -40,6 +40,7 @@ #ifndef __ARCH_NULL_REGISTERS_HH__ #define __ARCH_NULL_REGISTERS_HH__ +#include "arch/generic/vec_reg.hh" #include "arch/types.hh" #include "base/types.hh" @@ -52,6 +53,15 @@ typedef uint8_t CCReg; typedef uint64_t MiscReg; const RegIndex ZeroReg = 0; +// dummy typedefs since we don't have vector regs +constexpr unsigned NumVecElemPerVecReg = 2; +using VecElem = uint32_t; +using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; +using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; +using VecRegContainer = VecReg::Container; +// This has to be one to prevent warnings that are treated as errors +constexpr unsigned NumVecRegs = 1; + } #endif // __ARCH_NULL_REGISTERS_HH__ diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh index 475b4d2f8..edac96d59 100644 --- a/src/arch/power/isa.hh +++ b/src/arch/power/isa.hh @@ -101,6 +101,18 @@ class ISA : public SimObject return reg; } + int + flattenVecIndex(int reg) const + { + return reg; + } + + int + flattenVecElemIndex(int reg) const + { + return reg; + } + // dummy int flattenCCIndex(int reg) const diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh index 742809db1..4e8c9e9f4 100644 --- a/src/arch/power/registers.hh +++ b/src/arch/power/registers.hh @@ -31,6 +31,7 @@ #ifndef __ARCH_POWER_REGISTERS_HH__ #define __ARCH_POWER_REGISTERS_HH__ +#include "arch/generic/vec_reg.hh" #include "arch/power/generated/max_inst_regs.hh" #include "arch/power/miscregs.hh" @@ -53,6 +54,15 @@ typedef uint64_t MiscReg; // dummy typedef since we don't have CC regs typedef uint8_t CCReg; +// dummy typedefs since we don't have vector regs +constexpr unsigned NumVecElemPerVecReg = 2; +using VecElem = uint32_t; +using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; +using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; +using VecRegContainer = VecReg::Container; +// This has to be one to prevent warnings that are treated as errors +constexpr unsigned NumVecRegs = 1; + // Constants Related to the number of registers const int NumIntArchRegs = 32; diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh index 3f2412303..578057aa0 100644 --- a/src/arch/riscv/isa.hh +++ b/src/arch/riscv/isa.hh @@ -97,6 +97,18 @@ class ISA : public SimObject return reg; } + int + flattenVecIndex(int reg) const + { + return reg; + } + + int + flattenVecElemIndex(int reg) const + { + return reg; + } + // dummy int flattenCCIndex(int reg) const diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh index 2666784e5..6ae1c1691 100644 --- a/src/arch/riscv/registers.hh +++ b/src/arch/riscv/registers.hh @@ -51,6 +51,7 @@ #include <string> #include "arch/generic/types.hh" +#include "arch/generic/vec_reg.hh" #include "arch/isa_traits.hh" #include "arch/riscv/generated/max_inst_regs.hh" #include "base/types.hh" @@ -67,10 +68,19 @@ typedef double FloatReg; typedef uint8_t CCReg; // Not applicable to Riscv typedef uint64_t MiscReg; +// dummy typedefs since we don't have vector regs +const unsigned NumVecElemPerVecReg = 2; +using VecElem = uint32_t; +using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; +using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; +using VecRegContainer = VecReg::Container; + const int NumIntArchRegs = 32; const int NumMicroIntRegs = 1; const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs; const int NumFloatRegs = 32; +// This has to be one to prevent warnings that are treated as errors +const unsigned NumVecRegs = 1; const int NumCCRegs = 0; const int NumMiscRegs = 4096; diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh index ded5b34ff..82fee0d00 100644 --- a/src/arch/sparc/isa.hh +++ b/src/arch/sparc/isa.hh @@ -202,6 +202,8 @@ class ISA : public SimObject return RegId(CCRegClass, flattenCCIndex(regId.index())); case MiscRegClass: return RegId(MiscRegClass, flattenMiscIndex(regId.index())); + default: + break; } return regId; } @@ -221,6 +223,18 @@ class ISA : public SimObject return reg; } + int + flattenVecIndex(int reg) const + { + return reg; + } + + int + flattenVecElemIndex(int reg) const + { + return reg; + } + // dummy int flattenCCIndex(int reg) const diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh index 62c876f3d..596fdf4d0 100644 --- a/src/arch/sparc/registers.hh +++ b/src/arch/sparc/registers.hh @@ -32,6 +32,7 @@ #ifndef __ARCH_SPARC_REGISTERS_HH__ #define __ARCH_SPARC_REGISTERS_HH__ +#include "arch/generic/vec_reg.hh" #include "arch/sparc/generated/max_inst_regs.hh" #include "arch/sparc/miscregs.hh" #include "arch/sparc/sparc_traits.hh" @@ -52,6 +53,15 @@ typedef uint32_t FloatRegBits; // dummy typedef since we don't have CC regs typedef uint8_t CCReg; +// dummy typedefs since we don't have vector regs +constexpr unsigned NumVecElemPerVecReg = 2; +using VecElem = uint32_t; +using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; +using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; +using VecRegContainer = VecReg::Container; +// This has to be one to prevent warnings that are treated as errors +constexpr unsigned NumVecRegs = 1; + typedef union { IntReg intReg; diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh index 099d27c7c..b61face09 100644 --- a/src/arch/x86/isa.hh +++ b/src/arch/x86/isa.hh @@ -82,6 +82,8 @@ namespace X86ISA return RegId(CCRegClass, flattenCCIndex(regId.index())); case MiscRegClass: return RegId(MiscRegClass, flattenMiscIndex(regId.index())); + default: + break; } return regId; } @@ -103,6 +105,18 @@ namespace X86ISA } int + flattenVecIndex(int reg) const + { + return reg; + } + + int + flattenVecElemIndex(int reg) const + { + return reg; + } + + int flattenCCIndex(int reg) const { return reg; diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh index d23731977..9db3349f0 100644 --- a/src/arch/x86/registers.hh +++ b/src/arch/x86/registers.hh @@ -41,6 +41,7 @@ #ifndef __ARCH_X86_REGISTERS_HH__ #define __ARCH_X86_REGISTERS_HH__ +#include "arch/generic/vec_reg.hh" #include "arch/x86/generated/max_inst_regs.hh" #include "arch/x86/regs/int.hh" #include "arch/x86/regs/ccr.hh" @@ -93,6 +94,15 @@ typedef uint64_t IntReg; typedef uint64_t CCReg; typedef uint64_t MiscReg; +// dummy typedefs since we don't have vector regs +constexpr unsigned NumVecElemPerVecReg = 2; +using VecElem = uint32_t; +using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; +using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; +using VecRegContainer = VecReg::Container; +// This has to be one to prevent warnings that are treated as errors +constexpr unsigned NumVecRegs = 1; + //These floating point types are correct for mmx, but not //technically for x87 (80 bits) or at all for xmm (128 bits) typedef double FloatReg; |