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-rw-r--r--src/arch/generic/debugfaults.hh111
-rw-r--r--src/arch/x86/isa/includes.isa1
-rw-r--r--src/arch/x86/isa/microops/debug.isa67
3 files changed, 142 insertions, 37 deletions
diff --git a/src/arch/generic/debugfaults.hh b/src/arch/generic/debugfaults.hh
new file mode 100644
index 000000000..acffadc34
--- /dev/null
+++ b/src/arch/generic/debugfaults.hh
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2010 Advanced Micro Devices
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_GENERIC_DEBUGFAULTS_HH__
+#define __ARCH_GENERIC_DEBUGFAULTS_HH__
+
+#include "base/misc.hh"
+#include "sim/faults.hh"
+
+#include <string>
+
+namespace GenericISA
+{
+class M5DebugFault : public FaultBase
+{
+ public:
+ enum DebugFunc
+ {
+ PanicFunc,
+ FatalFunc,
+ WarnFunc,
+ WarnOnceFunc
+ };
+
+ protected:
+ std::string message;
+ DebugFunc func;
+
+ public:
+ M5DebugFault(DebugFunc _func, std::string _message) :
+ message(_message), func(_func)
+ {}
+
+ FaultName
+ name() const
+ {
+ switch (func) {
+ case PanicFunc:
+ return "panic fault";
+ case FatalFunc:
+ return "fatal fault";
+ case WarnFunc:
+ return "warn fault";
+ case WarnOnceFunc:
+ return "warn_once fault";
+ default:
+ panic("unrecognized debug function number\n");
+ }
+ }
+
+ void
+ invoke(ThreadContext *tc,
+ StaticInstPtr inst = StaticInst::nullStaticInstPtr)
+ {
+ switch (func) {
+ case PanicFunc:
+ panic(message);
+ break;
+ case FatalFunc:
+ fatal(message);
+ break;
+ case WarnFunc:
+ warn(message);
+ break;
+ case WarnOnceFunc:
+ warn_once(message);
+ break;
+ default:
+ panic("unrecognized debug function number\n");
+ }
+ }
+};
+} // namespace GenericISA
+
+#endif // __ARCH_GENERIC_DEBUGFAULTS_HH__
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 58b1fbc62..32708043e 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -53,6 +53,7 @@ output header {{
#include <sstream>
#include <iostream>
+#include "arch/generic/debugfaults.hh"
#include "arch/x86/emulenv.hh"
#include "arch/x86/insts/macroop.hh"
#include "arch/x86/insts/microfpop.hh"
diff --git a/src/arch/x86/isa/microops/debug.isa b/src/arch/x86/isa/microops/debug.isa
index 4b2ecdd5a..c2735565d 100644
--- a/src/arch/x86/isa/microops/debug.isa
+++ b/src/arch/x86/isa/microops/debug.isa
@@ -45,16 +45,29 @@ output header {{
class MicroDebugBase : public X86ISA::X86MicroopBase
{
protected:
+ typedef GenericISA::M5DebugFault::DebugFunc DebugFunc;
+ DebugFunc func;
std::string message;
uint8_t cc;
public:
- MicroDebugBase(ExtMachInst _machInst, const char * mnem,
+ MicroDebugBase(ExtMachInst machInst, const char * mnem,
const char * instMnem, uint64_t setFlags,
- std::string _message, uint8_t _cc);
+ DebugFunc _func, std::string _message, uint8_t _cc) :
+ X86MicroopBase(machInst, mnem, instMnem, setFlags, No_OpClass),
+ func(_func), message(_message), cc(_cc)
+ {}
- std::string generateDisassembly(Addr pc,
- const SymbolTable *symtab) const;
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream response;
+
+ printMnemonic(response, instMnem, mnemonic);
+ response << "\"" << message << "\"";
+
+ return response.str();
+ }
};
}};
@@ -70,53 +83,31 @@ def template MicroDebugDeclare {{
}};
def template MicroDebugExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault
+ %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
%(op_decl)s
%(op_rd)s
if (%(cond_test)s) {
- %(func)s("%s\n", message);
+ return new GenericISA::M5DebugFault(func, message);
+ } else {
+ return NoFault;
}
- return NoFault;
}
}};
-output decoder {{
- inline MicroDebugBase::MicroDebugBase(
- ExtMachInst machInst, const char * mnem, const char * instMnem,
- uint64_t setFlags, std::string _message, uint8_t _cc) :
- X86MicroopBase(machInst, mnem, instMnem,
- setFlags, No_OpClass),
- message(_message), cc(_cc)
- {
- }
-}};
-
def template MicroDebugConstructor {{
inline %(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
std::string _message, uint8_t _cc) :
%(base_class)s(machInst, "%(func)s", instMnem,
- setFlags, _message, _cc)
+ setFlags, %(func_num)s, _message, _cc)
{
%(constructor)s;
}
}};
-output decoder {{
- std::string MicroDebugBase::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- std::stringstream response;
-
- printMnemonic(response, instMnem, mnemonic);
- response << "\"" << message << "\"";
-
- return response.str();
- }
-}};
-
let {{
class MicroDebug(X86Microop):
def __init__(self, message, flags=None):
@@ -142,13 +133,14 @@ let {{
header_output = ""
decoder_output = ""
- def buildDebugMicro(func):
+ def buildDebugMicro(func, func_num):
global exec_output, header_output, decoder_output
iop = InstObjParams(func, "Micro%sFlags" % func.capitalize(),
"MicroDebugBase",
{"code": "",
"func": func,
+ "func_num": "GenericISA::M5DebugFault::%s" % func_num,
"cond_test": "checkCondition(ccFlagBits, cc)"})
exec_output += MicroDebugExecute.subst(iop)
header_output += MicroDebugDeclare.subst(iop)
@@ -158,6 +150,7 @@ let {{
"MicroDebugBase",
{"code": "",
"func": func,
+ "func_num": "GenericISA::M5DebugFault::%s" % func_num,
"cond_test": "true"})
exec_output += MicroDebugExecute.subst(iop)
header_output += MicroDebugDeclare.subst(iop)
@@ -169,8 +162,8 @@ let {{
global microopClasses
microopClasses[func] = MicroDebugChild
- buildDebugMicro("panic")
- buildDebugMicro("fatal")
- buildDebugMicro("warn")
- buildDebugMicro("warn_once")
+ buildDebugMicro("panic", "PanicFunc")
+ buildDebugMicro("fatal", "FatalFunc")
+ buildDebugMicro("warn", "WarnFunc")
+ buildDebugMicro("warn_once", "WarnOnceFunc")
}};
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 03:02:34 +0000