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-rw-r--r--src/arch/alpha/interrupts.hh28
-rw-r--r--src/arch/alpha/tlb.cc2
2 files changed, 17 insertions, 13 deletions
diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index 75031ae47..a86fb2d7b 100644
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -49,6 +49,7 @@ namespace AlphaISA
{
memset(interrupts, 0, sizeof(interrupts));
intstatus = 0;
+ newInfoSet = false;
}
void post(int int_num, int index)
@@ -137,18 +138,10 @@ namespace AlphaISA
}
if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) {
- tc->setMiscReg(IPR_ISR, summary);
- tc->setMiscReg(IPR_INTID, ipl);
-
- /* The following needs to be added back in somehow */
- // Checker needs to know these two registers were updated.
-/*#if USE_CHECKER
- if (this->checker) {
- this->checker->threadBase()->setMiscReg(IPR_ISR, summary);
- this->checker->threadBase()->setMiscReg(IPR_INTID, ipl);
- }
-#endif*/
-
+// assert(!newInfoSet);
+ newIpl = ipl;
+ newSummary = newSummary;
+ newInfoSet = true;
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
tc->readMiscReg(IPR_IPLR), ipl, summary);
@@ -158,7 +151,18 @@ namespace AlphaISA
}
}
+ void updateIntrInfo(ThreadContext *tc)
+ {
+ assert(newInfoSet);
+ tc->setMiscReg(IPR_ISR, newSummary);
+ tc->setMiscReg(IPR_INTID, newIpl);
+ newInfoSet = false;
+ }
+
private:
+ bool newInfoSet;
+ int newIpl;
+ int newSummary;
};
}
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index ae302e686..af69e45c0 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -292,7 +292,7 @@ namespace AlphaISA
Fault
ITB::translate(RequestPtr &req, ThreadContext *tc) const
{
- if (PcPAL(req->getVaddr())) {
+ if (PcPAL(req->getPC())) {
// strip off PAL PC marker (lsb is 1)
req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
hits++;