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-rw-r--r--src/arch/sparc/isa.cc1
-rw-r--r--src/arch/sparc/tlb.cc3
-rw-r--r--src/arch/sparc/ua2005.cc1
3 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index f6b941e2d..3456029c4 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -480,6 +480,7 @@ ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
break;
case MISCREG_HINTP:
hintp = val;
+ break;
case MISCREG_HTBA:
htba = val;
break;
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index f4564c6fd..49b353a7c 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -36,6 +36,7 @@
#include "arch/sparc/faults.hh"
#include "arch/sparc/registers.hh"
#include "base/bitfield.hh"
+#include "base/compiler.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
@@ -1155,6 +1156,7 @@ TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
break;
case ASI_ITLB_DATA_ACCESS_REG:
entry_insert = bits(va, 8,3);
+ M5_FALLTHROUGH;
case ASI_ITLB_DATA_IN_REG:
assert(entry_insert != -1 || mbits(va,10,9) == va);
ta_insert = itb->tag_access;
@@ -1169,6 +1171,7 @@ TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
break;
case ASI_DTLB_DATA_ACCESS_REG:
entry_insert = bits(va, 8,3);
+ M5_FALLTHROUGH;
case ASI_DTLB_DATA_IN_REG:
assert(entry_insert != -1 || mbits(va,10,9) == va);
ta_insert = tag_access;
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 274301b37..d8af29b91 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -137,6 +137,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
case MISCREG_PSTATE:
setMiscRegNoEffect(miscReg, val);
+ break;
case MISCREG_PIL:
setMiscRegNoEffect(miscReg, val);