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-rw-r--r--src/arch/SConscript2
-rw-r--r--src/arch/alpha/isa/decoder.isa10
-rw-r--r--src/arch/alpha/isa/fp.isa30
-rw-r--r--src/arch/alpha/isa/main.isa28
-rw-r--r--src/arch/alpha/isa/pal.isa8
-rw-r--r--src/arch/arm/isa_traits.hh2
-rw-r--r--src/arch/arm/linux/linux.cc50
-rw-r--r--src/arch/arm/tlb.hh6
-rw-r--r--src/arch/mips/SConscript6
-rw-r--r--src/arch/mips/isa/bitfields.isa22
-rw-r--r--src/arch/mips/isa/decoder.isa4
-rw-r--r--src/arch/sparc/isa/base.isa2
-rw-r--r--src/arch/sparc/isa/bitfields.isa72
-rw-r--r--src/arch/sparc/isa/formats/integerop.isa2
-rw-r--r--src/arch/sparc/isa/operands.isa186
-rw-r--r--src/arch/x86/bios/SConscript4
16 files changed, 217 insertions, 217 deletions
diff --git a/src/arch/SConscript b/src/arch/SConscript
index dd337b1b7..620de4d1c 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -45,7 +45,7 @@ Import('*')
isa_switch_hdrs = Split('''
faults.hh
interrupts.hh
- isa.hh
+ isa.hh
isa_traits.hh
kernel_stats.hh
locked_mem.hh
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 36458a047..d829ad744 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -100,7 +100,7 @@ decode OPCODE default Unknown::unknown() {
format IntegerOperate {
- 0x10: decode INTFUNC { // integer arithmetic operations
+ 0x10: decode INTFUNC { // integer arithmetic operations
0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
0x40: addlv({{
@@ -173,7 +173,7 @@ decode OPCODE default Unknown::unknown() {
}});
}
- 0x11: decode INTFUNC { // integer logical operations
+ 0x11: decode INTFUNC { // integer logical operations
0x00: and({{ Rc = Ra & Rb_or_imm; }});
0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
@@ -291,7 +291,7 @@ decode OPCODE default Unknown::unknown() {
}});
}
- 0x13: decode INTFUNC { // integer multiplies
+ 0x13: decode INTFUNC { // integer multiplies
0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp);
0x30: umulh({{
@@ -301,7 +301,7 @@ decode OPCODE default Unknown::unknown() {
}}, IntMultOp);
0x40: mullv({{
// 32-bit multiply with trap on overflow
- int64_t Rax = Ra.sl; // sign extended version of Ra.sl
+ int64_t Rax = Ra.sl; // sign extended version of Ra.sl
int64_t Rbx = Rb_or_imm.sl;
int64_t tmp = Rax * Rbx;
// To avoid overflow, all the upper 32 bits must match
@@ -587,7 +587,7 @@ decode OPCODE default Unknown::unknown() {
format BasicOperateWithNopCheck {
0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
- 0x014: FailUnimpl::itoff(); // VAX-format conversion
+ 0x014: FailUnimpl::itoff(); // VAX-format conversion
}
}
}
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index f9abd9b68..b1d01724d 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -32,9 +32,9 @@
//
// Floating-point instructions
//
-// Note that many FP-type instructions which do not support all the
-// various rounding & trapping modes use the simpler format
-// BasicOperateWithNopCheck.
+// Note that many FP-type instructions which do not support all the
+// various rounding & trapping modes use the simpler format
+// BasicOperateWithNopCheck.
//
output exec {{
@@ -45,7 +45,7 @@ output exec {{
#if FULL_SYSTEM
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
- Fault fault = NoFault; // dummy... this ipr access should not fault
+ Fault fault = NoFault; // dummy... this ipr access should not fault
if (!ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
fault = new FloatEnableFault;
}
@@ -71,11 +71,11 @@ output header {{
public:
/// Alpha FP rounding modes.
enum RoundingMode {
- Chopped = 0, ///< round toward zero
+ Chopped = 0, ///< round toward zero
Minus_Infinity = 1, ///< round toward minus infinity
- Normal = 2, ///< round to nearest (default)
- Dynamic = 3, ///< use FPCR setting (in instruction)
- Plus_Infinity = 3 ///< round to plus inifinity (in FPCR)
+ Normal = 2, ///< round to nearest (default)
+ Dynamic = 3, ///< use FPCR setting (in instruction)
+ Plus_Infinity = 3 ///< round to plus inifinity (in FPCR)
};
/// Alpha FP trapping modes.
@@ -84,10 +84,10 @@ output header {{
/// the assembly modifier is V rather than U.
enum TrappingMode {
/// default: nothing enabled
- Imprecise = 0, ///< no modifier
+ Imprecise = 0, ///< no modifier
/// underflow/overflow traps enabled, inexact disabled
- Underflow_Imprecise = 1, ///< /U or /V
- Underflow_Precise = 5, ///< /SU or /SV
+ Underflow_Imprecise = 1, ///< /U or /V
+ Underflow_Precise = 5, ///< /SU or /SV
/// underflow/overflow and inexact traps enabled
Underflow_Inexact_Precise = 7 ///< /SUI or /SVI
};
@@ -192,10 +192,10 @@ output decoder {{
}
const int AlphaFP::alphaToC99RoundingMode[] = {
- M5_FE_TOWARDZERO, // Chopped
- M5_FE_DOWNWARD, // Minus_Infinity
- M5_FE_TONEAREST, // Normal
- M5_FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
+ M5_FE_TOWARDZERO, // Chopped
+ M5_FE_DOWNWARD, // Minus_Infinity
+ M5_FE_TONEAREST, // Normal
+ M5_FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
};
const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index fa0086fc7..077520139 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -102,30 +102,30 @@ namespace AlphaISA;
// Universal (format-independent) fields
def bitfield PALMODE <32:32>;
-def bitfield OPCODE <31:26>;
-def bitfield RA <25:21>;
-def bitfield RB <20:16>;
+def bitfield OPCODE <31:26>;
+def bitfield RA <25:21>;
+def bitfield RB <20:16>;
// Memory format
def signed bitfield MEMDISP <15: 0>; // displacement
def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
// Memory-format jumps
-def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
-def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
+def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
+def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
// Branch format
def signed bitfield BRDISP <20: 0>; // displacement
// Integer operate format(s>;
-def bitfield INTIMM <20:13>; // integer immediate (literal)
-def bitfield IMM <12:12>; // immediate flag
-def bitfield INTFUNC <11: 5>; // function code
-def bitfield RC < 4: 0>; // dest reg
+def bitfield INTIMM <20:13>; // integer immediate (literal)
+def bitfield IMM <12:12>; // immediate flag
+def bitfield INTFUNC <11: 5>; // function code
+def bitfield RC < 4: 0>; // dest reg
// Floating-point operate format
-def bitfield FA <25:21>;
-def bitfield FB <20:16>;
+def bitfield FA <25:21>;
+def bitfield FB <20:16>;
def bitfield FP_FULLFUNC <15: 5>; // complete function code
def bitfield FP_TRAPMODE <15:13>; // trapping mode
def bitfield FP_ROUNDMODE <12:11>; // rounding mode
@@ -133,10 +133,10 @@ def bitfield FP_FULLFUNC <15: 5>; // complete function code
def bitfield FP_SRCTYPE <10: 9>; // source reg type
def bitfield FP_SHORTFUNC < 8: 5>; // short function code
def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
-def bitfield FC < 4: 0>; // dest reg
+def bitfield FC < 4: 0>; // dest reg
// PALcode format
-def bitfield PALFUNC <25: 0>; // function code
+def bitfield PALFUNC <25: 0>; // function code
// EV5 PAL instructions:
// HW_LD/HW_ST
@@ -154,7 +154,7 @@ def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
def bitfield HW_REI_MBZ <13: 0>; // must be zero
// HW_MTPR/MW_MFPR
-def bitfield HW_IPR_IDX <15:0>; // IPR index
+def bitfield HW_IPR_IDX <15:0>; // IPR index
// M5 instructions
def bitfield M5FUNC <7:0>;
diff --git a/src/arch/alpha/isa/pal.isa b/src/arch/alpha/isa/pal.isa
index c6c0fa95c..53e0d6193 100644
--- a/src/arch/alpha/isa/pal.isa
+++ b/src/arch/alpha/isa/pal.isa
@@ -84,10 +84,10 @@ output header {{
class CallPalBase : public AlphaStaticInst
{
protected:
- int palFunc; ///< Function code part of instruction
- int palOffset; ///< Target PC, offset from IPR_PAL_BASE
- bool palValid; ///< is the function code valid?
- bool palPriv; ///< is this call privileged?
+ int palFunc; ///< Function code part of instruction
+ int palOffset; ///< Target PC, offset from IPR_PAL_BASE
+ bool palValid; ///< is the function code valid?
+ bool palPriv; ///< is this call privileged?
/// Constructor.
CallPalBase(const char *mnem, ExtMachInst _machInst,
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index f6aa7fcf0..a24852ba9 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -99,7 +99,7 @@ namespace ArmISA
// return a no-op instruction... used for instruction fetch faults
const ExtMachInst NoopMachInst = 0x00000000;
- const int LogVMPageSize = 12; // 4K bytes
+ const int LogVMPageSize = 12; // 4K bytes
const int VMPageSize = (1 << LogVMPageSize);
// Shouldn't this be 1 because of Thumb?! Dynamic? --Ali
diff --git a/src/arch/arm/linux/linux.cc b/src/arch/arm/linux/linux.cc
index c81eee3c8..a26567475 100644
--- a/src/arch/arm/linux/linux.cc
+++ b/src/arch/arm/linux/linux.cc
@@ -36,49 +36,49 @@
// open(2) flags translation table
OpenFlagTransTable ArmLinux::openFlagTable[] = {
#ifdef _MSC_VER
- { ArmLinux::TGT_O_RDONLY, _O_RDONLY },
- { ArmLinux::TGT_O_WRONLY, _O_WRONLY },
- { ArmLinux::TGT_O_RDWR, _O_RDWR },
- { ArmLinux::TGT_O_APPEND, _O_APPEND },
- { ArmLinux::TGT_O_CREAT, _O_CREAT },
- { ArmLinux::TGT_O_TRUNC, _O_TRUNC },
- { ArmLinux::TGT_O_EXCL, _O_EXCL },
+ { ArmLinux::TGT_O_RDONLY, _O_RDONLY },
+ { ArmLinux::TGT_O_WRONLY, _O_WRONLY },
+ { ArmLinux::TGT_O_RDWR, _O_RDWR },
+ { ArmLinux::TGT_O_APPEND, _O_APPEND },
+ { ArmLinux::TGT_O_CREAT, _O_CREAT },
+ { ArmLinux::TGT_O_TRUNC, _O_TRUNC },
+ { ArmLinux::TGT_O_EXCL, _O_EXCL },
#ifdef _O_NONBLOCK
- { ArmLinux::TGT_O_NONBLOCK, _O_NONBLOCK },
+ { ArmLinux::TGT_O_NONBLOCK, _O_NONBLOCK },
#endif
#ifdef _O_NOCTTY
- { ArmLinux::TGT_O_NOCTTY, _O_NOCTTY },
+ { ArmLinux::TGT_O_NOCTTY, _O_NOCTTY },
#endif
#ifdef _O_SYNC
- { ArmLinux::TGT_O_SYNC, _O_SYNC },
+ { ArmLinux::TGT_O_SYNC, _O_SYNC },
#endif
#else /* !_MSC_VER */
- { ArmLinux::TGT_O_RDONLY, O_RDONLY },
- { ArmLinux::TGT_O_WRONLY, O_WRONLY },
- { ArmLinux::TGT_O_RDWR, O_RDWR },
- { ArmLinux::TGT_O_CREAT, O_CREAT },
- { ArmLinux::TGT_O_EXCL, O_EXCL },
- { ArmLinux::TGT_O_NOCTTY, O_NOCTTY },
- { ArmLinux::TGT_O_TRUNC, O_TRUNC },
- { ArmLinux::TGT_O_APPEND, O_APPEND },
- { ArmLinux::TGT_O_NONBLOCK, O_NONBLOCK },
+ { ArmLinux::TGT_O_RDONLY, O_RDONLY },
+ { ArmLinux::TGT_O_WRONLY, O_WRONLY },
+ { ArmLinux::TGT_O_RDWR, O_RDWR },
+ { ArmLinux::TGT_O_CREAT, O_CREAT },
+ { ArmLinux::TGT_O_EXCL, O_EXCL },
+ { ArmLinux::TGT_O_NOCTTY, O_NOCTTY },
+ { ArmLinux::TGT_O_TRUNC, O_TRUNC },
+ { ArmLinux::TGT_O_APPEND, O_APPEND },
+ { ArmLinux::TGT_O_NONBLOCK, O_NONBLOCK },
#ifdef O_SYNC
- { ArmLinux::TGT_O_SYNC, O_SYNC },
+ { ArmLinux::TGT_O_SYNC, O_SYNC },
#endif
#ifdef FASYNC
- { ArmLinux::TGT_FASYNC, FASYNC },
+ { ArmLinux::TGT_FASYNC, FASYNC },
#endif
#ifdef O_DIRECT
- { ArmLinux::TGT_O_DIRECT, O_DIRECT },
+ { ArmLinux::TGT_O_DIRECT, O_DIRECT },
#endif
#ifdef O_LARGEFILE
- { ArmLinux::TGT_O_LARGEFILE, O_LARGEFILE },
+ { ArmLinux::TGT_O_LARGEFILE, O_LARGEFILE },
#endif
#ifdef O_DIRECTORY
- { ArmLinux::TGT_O_DIRECTORY, O_DIRECTORY },
+ { ArmLinux::TGT_O_DIRECTORY, O_DIRECTORY },
#endif
#ifdef O_NOFOLLOW
- { ArmLinux::TGT_O_NOFOLLOW, O_NOFOLLOW },
+ { ArmLinux::TGT_O_NOFOLLOW, O_NOFOLLOW },
#endif
#endif /* _MSC_VER */
};
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 21062ea0d..5b24eebe2 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -84,10 +84,10 @@ class TLB : public BaseTLB
};
protected:
- TlbEntry *table; // the Page Table
- int size; // TLB Size
+ TlbEntry *table; // the Page Table
+ int size; // TLB Size
- uint32_t _attr; // Memory attributes for last accessed TLB entry
+ uint32_t _attr; // Memory attributes for last accessed TLB entry
#if FULL_SYSTEM
TableWalker *tableWalker;
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index ffc1f18eb..9e0275de7 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -44,15 +44,15 @@ if env['TARGET_ISA'] == 'mips':
TraceFlag('MipsPRA')
if env['FULL_SYSTEM']:
- SimObject('MipsSystem.py')
- SimObject('MipsInterrupts.py')
+ SimObject('MipsSystem.py')
+ SimObject('MipsInterrupts.py')
Source('idle_event.cc')
Source('mips_core_specific.cc')
Source('vtophys.cc')
Source('system.cc')
Source('stacktrace.cc')
Source('linux/system.cc')
- Source('interrupts.cc')
+ Source('interrupts.cc')
Source('bare_iron/system.cc')
else:
Source('process.cc')
diff --git a/src/arch/mips/isa/bitfields.isa b/src/arch/mips/isa/bitfields.isa
index 85d2d96da..d2d119cac 100644
--- a/src/arch/mips/isa/bitfields.isa
+++ b/src/arch/mips/isa/bitfields.isa
@@ -46,27 +46,27 @@ def bitfield FUNCTION < 5: 0>;
def bitfield FUNCTION_HI < 5: 3>;
def bitfield FUNCTION_LO < 2: 0>;
-def bitfield RS <25:21>;
+def bitfield RS <25:21>;
def bitfield RS_MSB <25:25>;
def bitfield RS_HI <25:24>;
def bitfield RS_LO <23:21>;
def bitfield RS_SRL <25:22>;
def bitfield RS_RT <25:16>;
-def bitfield RT <20:16>;
+def bitfield RT <20:16>;
def bitfield RT_HI <20:19>;
def bitfield RT_LO <18:16>;
def bitfield RT_RD <20:11>;
-def bitfield RD <15:11>;
+def bitfield RD <15:11>;
-def bitfield INTIMM <15: 0>;
+def bitfield INTIMM <15: 0>;
def bitfield RS_RT_INTIMM <25: 0>;
// Floating-point operate format
def bitfield FMT <25:21>;
def bitfield FR <25:21>;
-def bitfield FT <20:16>;
-def bitfield FS <15:11>;
-def bitfield FD <10:6>;
+def bitfield FT <20:16>;
+def bitfield FS <15:11>;
+def bitfield FD <10:6>;
def bitfield ND <17:17>;
def bitfield TF <16:16>;
@@ -90,15 +90,15 @@ def bitfield SC < 5: 5>;
def bitfield OFFSET <15: 0>; // displacement
// Jmp format
-def bitfield JMPTARG <25: 0>;
-def bitfield HINT <10: 6>;
+def bitfield JMPTARG <25: 0>;
+def bitfield HINT <10: 6>;
def bitfield SYSCALLCODE <25: 6>;
def bitfield TRAPCODE <15:13>;
// EXT/INS instructions
-def bitfield MSB <15:11>;
-def bitfield LSB <10: 6>;
+def bitfield MSB <15:11>;
+def bitfield LSB <10: 6>;
// M5 instructions
def bitfield M5FUNC <7:0>;
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 8a8033a00..173fa89df 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -1131,7 +1131,7 @@ decode OPCODE_HI default Unknown::unknown() {
UnorderedFalse);
0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }},
UnorderedTrue);
- 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }},
+ 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }},
UnorderedFalse);
0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }},
UnorderedTrue);
@@ -1252,7 +1252,7 @@ decode OPCODE_HI default Unknown::unknown() {
UnorderedFalse);
0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }},
UnorderedTrue);
- 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }},
+ 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }},
UnorderedFalse);
0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }},
UnorderedTrue);
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index af70acb3d..b95ffd69a 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -567,7 +567,7 @@ output exec {{
inline Fault
checkFpEnableFault(%(CPU_exec_context)s *xc)
{
- Fault fault = NoFault; // dummy... this ipr access should not fault
+ Fault fault = NoFault; // dummy... this ipr access should not fault
if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef &&
xc->readMiscReg(MISCREG_FPRS) & 0x4) {
return NoFault;
diff --git a/src/arch/sparc/isa/bitfields.isa b/src/arch/sparc/isa/bitfields.isa
index afa8f88a2..98f2068a0 100644
--- a/src/arch/sparc/isa/bitfields.isa
+++ b/src/arch/sparc/isa/bitfields.isa
@@ -36,48 +36,48 @@
// Bitfields are shared liberally between instruction formats, so they are
// simply defined alphabetically
-def bitfield A <29>;
+def bitfield A <29>;
def bitfield BPCC <21:20>; // for BPcc & FBPcc
def bitfield FCMPCC <26:25>; // for FCMP & FCMPEa
def bitfield FMOVCC <13:11>; // for FMOVcc
def bitfield CC <12:11>; // for MOVcc & Tcc
def bitfield MOVCC3 <18>; // also for MOVcc
-def bitfield CMASK <6:4>;
-def bitfield COND2 <28:25>;
-def bitfield COND4 <17:14>;
-def bitfield D16HI <21:20>;
-def bitfield D16LO <13:0>;
-def bitfield DISP19 <18:0>;
-def bitfield DISP22 <21:0>;
-def bitfield DISP30 <29:0>;
-def bitfield FCN <29:25>;
-def bitfield I <13>;
-def bitfield IMM_ASI <12:5>;
-def bitfield IMM22 <21:0>;
+def bitfield CMASK <6:4>;
+def bitfield COND2 <28:25>;
+def bitfield COND4 <17:14>;
+def bitfield D16HI <21:20>;
+def bitfield D16LO <13:0>;
+def bitfield DISP19 <18:0>;
+def bitfield DISP22 <21:0>;
+def bitfield DISP30 <29:0>;
+def bitfield FCN <29:25>;
+def bitfield I <13>;
+def bitfield IMM_ASI <12:5>;
+def bitfield IMM22 <21:0>;
def bitfield M5FUNC <15:7>;
-def bitfield MMASK <3:0>;
-def bitfield OP <31:30>;
-def bitfield OP2 <24:22>;
-def bitfield OP3 <24:19>;
-def bitfield OPF <13:5>;
-def bitfield OPF_CC <13:11>;
-def bitfield OPF_LOW5 <9:5>;
-def bitfield OPF_LOW6 <10:5>;
-def bitfield P <19>;
-def bitfield RCOND2 <27:25>;
-def bitfield RCOND3 <12:10>;
-def bitfield RCOND4 <12:10>;
-def bitfield RD <29:25>;
-def bitfield RS1 <18:14>;
-def bitfield RS2 <4:0>;
-def bitfield SHCNT32 <4:0>;
-def bitfield SHCNT64 <5:0>;
-def bitfield SIMM10 <9:0>;
-def bitfield SIMM11 <10:0>;
-def bitfield SIMM13 <12:0>;
-def bitfield SW_TRAP <7:0>;
-def bitfield X <12>;
+def bitfield MMASK <3:0>;
+def bitfield OP <31:30>;
+def bitfield OP2 <24:22>;
+def bitfield OP3 <24:19>;
+def bitfield OPF <13:5>;
+def bitfield OPF_CC <13:11>;
+def bitfield OPF_LOW5 <9:5>;
+def bitfield OPF_LOW6 <10:5>;
+def bitfield P <19>;
+def bitfield RCOND2 <27:25>;
+def bitfield RCOND3 <12:10>;
+def bitfield RCOND4 <12:10>;
+def bitfield RD <29:25>;
+def bitfield RS1 <18:14>;
+def bitfield RS2 <4:0>;
+def bitfield SHCNT32 <4:0>;
+def bitfield SHCNT64 <5:0>;
+def bitfield SIMM10 <9:0>;
+def bitfield SIMM11 <10:0>;
+def bitfield SIMM13 <12:0>;
+def bitfield SW_TRAP <7:0>;
+def bitfield X <12>;
// Extended bitfields which aren't part of the actual instruction.
-def bitfield EXT_ASI <39:32>;
+def bitfield EXT_ASI <39:32>;
diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa
index e9536f495..58d7b37ee 100644
--- a/src/arch/sparc/isa/formats/integerop.isa
+++ b/src/arch/sparc/isa/formats/integerop.isa
@@ -259,7 +259,7 @@ let {{
def doIntFormat(code, ccCode, name, Name, opt_flags):
(usesImm, code, immCode,
rString, iString) = splitOutImm(code)
- iop = InstObjParams(name, Name, 'IntOp',
+ iop = InstObjParams(name, Name, 'IntOp',
{"code": code, "cc_code": ccCode},
opt_flags)
header_output = BasicDeclare.subst(iop)
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index dfc71f419..047451ae7 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -72,71 +72,71 @@ def operands {{
# For clarity, descriptions that depend on unsigned behavior should
# explicitly specify '.uq'.
- 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
+ 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
# The Rd from the previous window
- 'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2),
+ 'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2),
# The Rd from the next window
- 'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3),
+ 'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3),
# For microcoded twin load instructions, RdTwin appears in the "code"
# for the instruction is replaced by RdLow or RdHigh by the format
# before it's processed by the iop.
# The low (even) register of a two register pair
- 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4),
+ 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4),
# The high (odd) register of a two register pair
- 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5),
- 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6),
- 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7),
+ 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5),
+ 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6),
+ 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7),
# A microcode register. Right now, this is the only one.
- 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8),
+ 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8),
# Because double and quad precision register numbers are decoded
# differently, they get different operands. The single precision versions
# have an s post pended to their name.
- 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
- #'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
- 'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
- 'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
+ 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
+ #'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
+ 'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
+ 'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
# Each Frd_N refers to the Nth double precision register from Frd.
# Note that this adds twice N to the register number.
- #'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
- 'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
- 'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
- #'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
- 'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10),
- 'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10),
- #'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
- 'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10),
- 'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10),
- #'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
- 'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10),
- 'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10),
- #'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
- 'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10),
- 'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10),
- #'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
- 'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10),
- 'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10),
- #'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
- 'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10),
- 'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10),
- #'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
- 'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10),
- 'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10),
- 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11),
- #'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
- 'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11),
- 'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11),
- 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12),
- #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
- 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12),
- 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12),
+ #'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
+ 'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
+ 'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
+ #'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
+ 'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10),
+ 'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10),
+ #'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
+ 'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10),
+ 'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10),
+ #'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
+ 'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10),
+ 'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10),
+ #'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
+ 'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10),
+ 'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10),
+ #'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
+ 'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10),
+ 'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10),
+ #'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
+ 'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10),
+ 'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10),
+ #'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
+ 'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10),
+ 'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10),
+ 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11),
+ #'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
+ 'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11),
+ 'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11),
+ 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12),
+ #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
+ 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12),
+ 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12),
'PC': ('PCState', 'udw', 'pc', (None, None, 'IsControl'), 30),
'NPC': ('PCState', 'udw', 'npc', (None, None, 'IsControl'), 30),
'NNPC': ('PCState', 'udw', 'nnpc', (None, None, 'IsControl'), 30),
# Registers which are used explicitly in instructions
- 'R0': ('IntReg', 'udw', '0', None, 6),
- 'R1': ('IntReg', 'udw', '1', None, 7),
- 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
- 'R16': ('IntReg', 'udw', '16', None, 9),
+ 'R0': ('IntReg', 'udw', '0', None, 6),
+ 'R1': ('IntReg', 'udw', '1', None, 7),
+ 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
+ 'R16': ('IntReg', 'udw', '16', None, 9),
'O0': ('IntReg', 'udw', '8', 'IsInteger', 10),
'O1': ('IntReg', 'udw', '9', 'IsInteger', 11),
'O2': ('IntReg', 'udw', '10', 'IsInteger', 12),
@@ -145,55 +145,55 @@ def operands {{
'O5': ('IntReg', 'udw', '13', 'IsInteger', 15),
# Control registers
-# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
-# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
- 'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40),
- 'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41),
- 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
- 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
- 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
- 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
-# 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46),
- 'Gsr': ('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46),
- 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
- 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
- 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),
- 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50),
- 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51),
- 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52),
+# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
+# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
+ 'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40),
+ 'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41),
+ 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
+ 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
+ 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
+ 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
+# 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46),
+ 'Gsr': ('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46),
+ 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
+ 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
+ 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),
+ 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50),
+ 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51),
+ 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52),
- 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53),
- 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),
- 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),
- 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56),
- 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
- 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
- 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
- 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
- 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
- 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62),
-# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
-# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
-# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
-# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
-# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
- 'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63),
- 'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64),
- 'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65),
- 'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66),
- 'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67),
+ 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53),
+ 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),
+ 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),
+ 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56),
+ 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
+ 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
+ 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
+ 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
+ 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
+ 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62),
+# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
+# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
+# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
+# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
+# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
+ 'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63),
+ 'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64),
+ 'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65),
+ 'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66),
+ 'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67),
'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68),
- 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
- 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
- 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
- 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
- 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
- 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
- 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),
+ 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
+ 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
+ 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
+ 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
+ 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
+ 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
+ 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),
- 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
+ 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
# Mem gets a large number so it's always last
- 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
+ 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
}};
diff --git a/src/arch/x86/bios/SConscript b/src/arch/x86/bios/SConscript
index 5fd70a538..16a413ed0 100644
--- a/src/arch/x86/bios/SConscript
+++ b/src/arch/x86/bios/SConscript
@@ -48,12 +48,12 @@ if env['TARGET_ISA'] == 'x86':
# The DMI tables.
SimObject('SMBios.py')
- Source('smbios.cc')
+ Source('smbios.cc')
# Intel Multiprocessor Specification Configuration Table
SimObject('IntelMP.py')
Source('intelmp.cc')
# ACPI system description tables
- SimObject('ACPI.py')
+ SimObject('ACPI.py')
Source('acpi.cc')
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 21:47:35 +0000