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-rw-r--r--src/arch/alpha/faults.cc44
-rw-r--r--src/arch/alpha/remote_gdb.cc77
-rw-r--r--src/arch/alpha/utility.cc30
-rw-r--r--src/arch/arm/faults.cc65
-rw-r--r--src/arch/arm/tlb.cc20
-rw-r--r--src/arch/arm/utility.cc78
-rw-r--r--src/arch/mips/tlb.cc34
-rw-r--r--src/arch/power/tlb.cc13
-rwxr-xr-xsrc/arch/power/vtophys.cc11
-rw-r--r--src/arch/sparc/faults.cc117
-rw-r--r--src/arch/sparc/utility.cc24
-rw-r--r--src/arch/x86/faults.cc80
12 files changed, 297 insertions, 296 deletions
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index a6d3ef2d0..e4a5c9223 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -187,16 +187,17 @@ ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
if (FullSystem) {
ItbFault::invoke(tc);
+ return;
+ }
+
+ Process *p = tc->getProcessPtr();
+ TlbEntry entry;
+ bool success = p->pTable->lookup(pc, entry);
+ if (!success) {
+ panic("Tried to execute unmapped address %#x.\n", pc);
} else {
- Process *p = tc->getProcessPtr();
- TlbEntry entry;
- bool success = p->pTable->lookup(pc, entry);
- if (!success) {
- panic("Tried to execute unmapped address %#x.\n", pc);
- } else {
- VAddr vaddr(pc);
- tc->getITBPtr()->insert(vaddr.page(), entry);
- }
+ VAddr vaddr(pc);
+ tc->getITBPtr()->insert(vaddr.page(), entry);
}
}
@@ -205,19 +206,20 @@ NDtbMissFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
if (FullSystem) {
DtbFault::invoke(tc, inst);
+ return;
+ }
+
+ Process *p = tc->getProcessPtr();
+ TlbEntry entry;
+ bool success = p->pTable->lookup(vaddr, entry);
+ if (!success) {
+ if (p->fixupStackFault(vaddr))
+ success = p->pTable->lookup(vaddr, entry);
+ }
+ if (!success) {
+ panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
} else {
- Process *p = tc->getProcessPtr();
- TlbEntry entry;
- bool success = p->pTable->lookup(vaddr, entry);
- if (!success) {
- if (p->fixupStackFault(vaddr))
- success = p->pTable->lookup(vaddr, entry);
- }
- if (!success) {
- panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
- } else {
- tc->getDTBPtr()->insert(vaddr.page(), entry);
- }
+ tc->getDTBPtr()->insert(vaddr.page(), entry);
}
}
diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc
index aaf9ecb3c..aa120686c 100644
--- a/src/arch/alpha/remote_gdb.cc
+++ b/src/arch/alpha/remote_gdb.cc
@@ -156,51 +156,50 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
bool
RemoteGDB::acc(Addr va, size_t len)
{
- if (FullSystem) {
- Addr last_va;
-
- va = TruncPage(va);
- last_va = RoundPage(va + len);
-
- do {
- if (IsK0Seg(va)) {
- if (va < (K0SegBase + pmem->size())) {
- DPRINTF(GDBAcc, "acc: Mapping is valid K0SEG <= "
- "%#x < K0SEG + size\n", va);
- return true;
- } else {
- DPRINTF(GDBAcc, "acc: Mapping invalid %#x "
- "> K0SEG + size\n", va);
- return false;
- }
- }
+ if (!FullSystem)
+ panic("acc function needs to be rewritten for SE mode\n");
- /**
- * This code says that all accesses to palcode (instruction
- * and data) are valid since there isn't a va->pa mapping
- * because palcode is accessed physically. At some point this
- * should probably be cleaned up but there is no easy way to
- * do it.
- */
+ Addr last_va;
- if (PcPAL(va) || va < 0x10000)
- return true;
+ va = TruncPage(va);
+ last_va = RoundPage(va + len);
- Addr ptbr = context->readMiscRegNoEffect(IPR_PALtemp20);
- PageTableEntry pte =
- kernel_pte_lookup(context->getPhysProxy(), ptbr, va);
- if (!pte.valid()) {
- DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va);
+ do {
+ if (IsK0Seg(va)) {
+ if (va < (K0SegBase + pmem->size())) {
+ DPRINTF(GDBAcc, "acc: Mapping is valid K0SEG <= "
+ "%#x < K0SEG + size\n", va);
+ return true;
+ } else {
+ DPRINTF(GDBAcc, "acc: Mapping invalid %#x "
+ "> K0SEG + size\n", va);
return false;
}
- va += PageBytes;
- } while (va < last_va);
+ }
- DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
- return true;
- } else {
- panic("acc function needs to be rewritten for SE mode\n");
- }
+ /**
+ * This code says that all accesses to palcode (instruction
+ * and data) are valid since there isn't a va->pa mapping
+ * because palcode is accessed physically. At some point this
+ * should probably be cleaned up but there is no easy way to
+ * do it.
+ */
+
+ if (PcPAL(va) || va < 0x10000)
+ return true;
+
+ Addr ptbr = context->readMiscRegNoEffect(IPR_PALtemp20);
+ PageTableEntry pte =
+ kernel_pte_lookup(context->getPhysProxy(), ptbr, va);
+ if (!pte.valid()) {
+ DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va);
+ return false;
+ }
+ va += PageBytes;
+ } while (va < last_va);
+
+ DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
+ return true;
}
/*
diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index efafec4bc..1bac650a0 100644
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -39,24 +39,24 @@ namespace AlphaISA {
uint64_t
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
{
- if (FullSystem) {
- const int NumArgumentRegs = 6;
- if (number < NumArgumentRegs) {
- if (fp)
- return tc->readFloatRegBits(16 + number);
- else
- return tc->readIntReg(16 + number);
- } else {
- Addr sp = tc->readIntReg(StackPointerReg);
- FSTranslatingPortProxy* vp = tc->getVirtProxy();
- uint64_t arg = vp->read<uint64_t>(sp +
- (number-NumArgumentRegs) * sizeof(uint64_t));
- return arg;
- }
- } else {
+ if (!FullSystem) {
panic("getArgument() is Full system only\n");
M5_DUMMY_RETURN;
}
+
+ const int NumArgumentRegs = 6;
+ if (number < NumArgumentRegs) {
+ if (fp)
+ return tc->readFloatRegBits(16 + number);
+ else
+ return tc->readIntReg(16 + number);
+ } else {
+ Addr sp = tc->readIntReg(StackPointerReg);
+ FSTranslatingPortProxy* vp = tc->getVirtProxy();
+ uint64_t arg = vp->read<uint64_t>(sp +
+ (number-NumArgumentRegs) * sizeof(uint64_t));
+ return arg;
+ }
}
void
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 52441e03f..061392f59 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -178,19 +178,20 @@ UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
{
if (FullSystem) {
ArmFault::invoke(tc, inst);
+ return;
+ }
+
+ // If the mnemonic isn't defined this has to be an unknown instruction.
+ assert(unknown || mnemonic != NULL);
+ if (disabled) {
+ panic("Attempted to execute disabled instruction "
+ "'%s' (inst 0x%08x)", mnemonic, machInst);
+ } else if (unknown) {
+ panic("Attempted to execute unknown instruction (inst 0x%08x)",
+ machInst);
} else {
- // If the mnemonic isn't defined this has to be an unknown instruction.
- assert(unknown || mnemonic != NULL);
- if (disabled) {
- panic("Attempted to execute disabled instruction "
- "'%s' (inst 0x%08x)", mnemonic, machInst);
- } else if (unknown) {
- panic("Attempted to execute unknown instruction (inst 0x%08x)",
- machInst);
- } else {
- panic("Attempted to execute unimplemented instruction "
- "'%s' (inst 0x%08x)", mnemonic, machInst);
- }
+ panic("Attempted to execute unimplemented instruction "
+ "'%s' (inst 0x%08x)", mnemonic, machInst);
}
}
@@ -199,19 +200,20 @@ SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
{
if (FullSystem) {
ArmFault::invoke(tc, inst);
- } else {
- // As of now, there isn't a 32 bit thumb version of this instruction.
- assert(!machInst.bigThumb);
- uint32_t callNum;
- callNum = tc->readIntReg(INTREG_R7);
- tc->syscall(callNum);
-
- // Advance the PC since that won't happen automatically.
- PCState pc = tc->pcState();
- assert(inst);
- inst->advancePC(pc);
- tc->pcState(pc);
+ return;
}
+
+ // As of now, there isn't a 32 bit thumb version of this instruction.
+ assert(!machInst.bigThumb);
+ uint32_t callNum;
+ callNum = tc->readIntReg(INTREG_R7);
+ tc->syscall(callNum);
+
+ // Advance the PC since that won't happen automatically.
+ PCState pc = tc->pcState();
+ assert(inst);
+ inst->advancePC(pc);
+ tc->pcState(pc);
}
template<class T>
@@ -252,13 +254,14 @@ template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
void
ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) {
DPRINTF(Faults, "Invoking ArmSev Fault\n");
- if (FullSystem) {
- // Set sev_mailbox to 1, clear the pending interrupt from remote
- // SEV execution and let pipeline continue as pcState is still
- // valid.
- tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
- tc->getCpuPtr()->clearInterrupt(INT_SEV, 0);
- }
+ if (!FullSystem)
+ return;
+
+ // Set sev_mailbox to 1, clear the pending interrupt from remote
+ // SEV execution and let pipeline continue as pcState is still
+ // valid.
+ tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
+ tc->getCpuPtr()->clearInterrupt(INT_SEV, 0);
}
// return via SUBS pc, lr, xxx; rfe, movs, ldm
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 6953090d0..b19ad5265 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -418,14 +418,12 @@ TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
}
}
- if (!FullSystem) {
- Addr paddr;
- Process *p = tc->getProcessPtr();
+ Addr paddr;
+ Process *p = tc->getProcessPtr();
- if (!p->pTable->translate(vaddr, paddr))
- return Fault(new GenericPageTableFault(vaddr));
- req->setPaddr(paddr);
- }
+ if (!p->pTable->translate(vaddr, paddr))
+ return Fault(new GenericPageTableFault(vaddr));
+ req->setPaddr(paddr);
return NoFault;
}
@@ -570,11 +568,9 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
}
}
- if (FullSystem) {
- if (!bootUncacheability &&
- ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr))
- req->setFlags(Request::UNCACHEABLE);
- }
+ if (!bootUncacheability &&
+ ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr))
+ req->setFlags(Request::UNCACHEABLE);
switch ( (dacr >> (te->domain * 2)) & 0x3) {
case 0:
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 42b5be181..ac81c7db6 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -63,48 +63,48 @@ initCPU(ThreadContext *tc, int cpuId)
uint64_t
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
{
- if (FullSystem) {
- if (size == (uint16_t)(-1))
- size = ArmISA::MachineBytes;
- if (fp)
- panic("getArgument(): Floating point arguments not implemented\n");
-
- if (number < NumArgumentRegs) {
- // If the argument is 64 bits, it must be in an even regiser
- // number. Increment the number here if it isn't even.
- if (size == sizeof(uint64_t)) {
- if ((number % 2) != 0)
- number++;
- // Read the two halves of the data. Number is inc here to
- // get the second half of the 64 bit reg.
- uint64_t tmp;
- tmp = tc->readIntReg(number++);
- tmp |= tc->readIntReg(number) << 32;
- return tmp;
- } else {
- return tc->readIntReg(number);
- }
- } else {
- Addr sp = tc->readIntReg(StackPointerReg);
- FSTranslatingPortProxy* vp = tc->getVirtProxy();
- uint64_t arg;
- if (size == sizeof(uint64_t)) {
- // If the argument is even it must be aligned
- if ((number % 2) != 0)
- number++;
- arg = vp->read<uint64_t>(sp +
- (number-NumArgumentRegs) * sizeof(uint32_t));
- // since two 32 bit args == 1 64 bit arg, increment number
+ if (!FullSystem) {
+ panic("getArgument() only implemented for full system mode.\n");
+ M5_DUMMY_RETURN
+ }
+
+ if (size == (uint16_t)(-1))
+ size = ArmISA::MachineBytes;
+ if (fp)
+ panic("getArgument(): Floating point arguments not implemented\n");
+
+ if (number < NumArgumentRegs) {
+ // If the argument is 64 bits, it must be in an even regiser
+ // number. Increment the number here if it isn't even.
+ if (size == sizeof(uint64_t)) {
+ if ((number % 2) != 0)
number++;
- } else {
- arg = vp->read<uint32_t>(sp +
- (number-NumArgumentRegs) * sizeof(uint32_t));
- }
- return arg;
+ // Read the two halves of the data. Number is inc here to
+ // get the second half of the 64 bit reg.
+ uint64_t tmp;
+ tmp = tc->readIntReg(number++);
+ tmp |= tc->readIntReg(number) << 32;
+ return tmp;
+ } else {
+ return tc->readIntReg(number);
}
} else {
- panic("getArgument() only implemented for full system mode.\n");
- M5_DUMMY_RETURN
+ Addr sp = tc->readIntReg(StackPointerReg);
+ FSTranslatingPortProxy* vp = tc->getVirtProxy();
+ uint64_t arg;
+ if (size == sizeof(uint64_t)) {
+ // If the argument is even it must be aligned
+ if ((number % 2) != 0)
+ number++;
+ arg = vp->read<uint64_t>(sp +
+ (number-NumArgumentRegs) * sizeof(uint32_t));
+ // since two 32 bit args == 1 64 bit arg, increment number
+ number++;
+ } else {
+ arg = vp->read<uint32_t>(sp +
+ (number-NumArgumentRegs) * sizeof(uint32_t));
+ }
+ return arg;
}
}
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index d28ef8231..cd6d47d1e 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -295,33 +295,31 @@ TLB::regStats()
Fault
TLB::translateInst(RequestPtr req, ThreadContext *tc)
{
- if (!FullSystem) {
- Process * p = tc->getProcessPtr();
+ if (FullSystem)
+ panic("translateInst not implemented in MIPS.\n");
- Fault fault = p->pTable->translate(req);
- if (fault != NoFault)
- return fault;
+ Process * p = tc->getProcessPtr();
- return NoFault;
- } else {
- panic("translateInst not implemented in MIPS.\n");
- }
+ Fault fault = p->pTable->translate(req);
+ if (fault != NoFault)
+ return fault;
+
+ return NoFault;
}
Fault
TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
{
- if (!FullSystem) {
- Process * p = tc->getProcessPtr();
+ if (FullSystem)
+ panic("translateData not implemented in MIPS.\n");
- Fault fault = p->pTable->translate(req);
- if (fault != NoFault)
- return fault;
+ Process * p = tc->getProcessPtr();
- return NoFault;
- } else {
- panic("translateData not implemented in MIPS.\n");
- }
+ Fault fault = p->pTable->translate(req);
+ if (fault != NoFault)
+ return fault;
+
+ return NoFault;
}
Fault
diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc
index 2148e875a..9f535e9e5 100644
--- a/src/arch/power/tlb.cc
+++ b/src/arch/power/tlb.cc
@@ -309,14 +309,13 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
Fault
TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
{
- if (FullSystem) {
+ if (FullSystem)
fatal("translate atomic not yet implemented in full system mode.\n");
- } else {
- if (mode == Execute)
- return translateInst(req, tc);
- else
- return translateData(req, tc, mode == Write);
- }
+
+ if (mode == Execute)
+ return translateInst(req, tc);
+ else
+ return translateData(req, tc, mode == Write);
}
void
diff --git a/src/arch/power/vtophys.cc b/src/arch/power/vtophys.cc
index 597f41b2f..b03f507fc 100755
--- a/src/arch/power/vtophys.cc
+++ b/src/arch/power/vtophys.cc
@@ -1,6 +1,5 @@
/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * Copyright (c) 2007 MIPS Technologies, Inc.
+ * Copyright (c) 2012 Google
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,9 +25,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Ali Saidi
- * Nathan Binkert
- * Jaidev Patwardhan
+ * Authors: Gabe Black
*/
#include "arch/power/vtophys.hh"
@@ -38,12 +35,12 @@ using namespace std;
Addr
PowerISA::vtophys(Addr vaddr)
{
- fatal("VTOPHYS: Unimplemented on POWER\n");
+ fatal("vtophys: Unimplemented on POWER\n");
}
Addr
PowerISA::vtophys(ThreadContext *tc, Addr addr)
{
- fatal("VTOPHYS: Unimplemented on POWER\n");
+ fatal("vtophys: Unimplemented on POWER\n");
}
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index a737b328d..e67b8c50e 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -624,17 +624,18 @@ FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
{
if (FullSystem) {
SparcFaultBase::invoke(tc, inst);
+ return;
+ }
+
+ Process *p = tc->getProcessPtr();
+ TlbEntry entry;
+ bool success = p->pTable->lookup(vaddr, entry);
+ if (!success) {
+ panic("Tried to execute unmapped address %#x.\n", vaddr);
} else {
- Process *p = tc->getProcessPtr();
- TlbEntry entry;
- bool success = p->pTable->lookup(vaddr, entry);
- if (!success) {
- panic("Tried to execute unmapped address %#x.\n", vaddr);
- } else {
- Addr alignedVaddr = p->pTable->pageAlign(vaddr);
- tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
- p->M5_pid /*context id*/, false, entry.pte);
- }
+ Addr alignedVaddr = p->pTable->pageAlign(vaddr);
+ tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
+ p->M5_pid /*context id*/, false, entry.pte);
}
}
@@ -643,21 +644,22 @@ FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
{
if (FullSystem) {
SparcFaultBase::invoke(tc, inst);
+ return;
+ }
+
+ Process *p = tc->getProcessPtr();
+ TlbEntry entry;
+ bool success = p->pTable->lookup(vaddr, entry);
+ if (!success) {
+ if (p->fixupStackFault(vaddr))
+ success = p->pTable->lookup(vaddr, entry);
+ }
+ if (!success) {
+ panic("Tried to access unmapped address %#x.\n", vaddr);
} else {
- Process *p = tc->getProcessPtr();
- TlbEntry entry;
- bool success = p->pTable->lookup(vaddr, entry);
- if (!success) {
- if (p->fixupStackFault(vaddr))
- success = p->pTable->lookup(vaddr, entry);
- }
- if (!success) {
- panic("Tried to access unmapped address %#x.\n", vaddr);
- } else {
- Addr alignedVaddr = p->pTable->pageAlign(vaddr);
- tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
- p->M5_pid /*context id*/, false, entry.pte);
- }
+ Addr alignedVaddr = p->pTable->pageAlign(vaddr);
+ tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
+ p->M5_pid /*context id*/, false, entry.pte);
}
}
@@ -666,18 +668,19 @@ SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
{
if (FullSystem) {
SparcFaultBase::invoke(tc, inst);
- } else {
- doNormalFault(tc, trapType(), false);
+ return;
+ }
- Process *p = tc->getProcessPtr();
+ doNormalFault(tc, trapType(), false);
- //XXX This will only work in faults from a SparcLiveProcess
- SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
- assert(lp);
+ Process *p = tc->getProcessPtr();
- // Then adjust the PC and NPC
- tc->pcState(lp->readSpillStart());
- }
+ //XXX This will only work in faults from a SparcLiveProcess
+ SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
+ assert(lp);
+
+ // Then adjust the PC and NPC
+ tc->pcState(lp->readSpillStart());
}
void
@@ -685,18 +688,19 @@ FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
{
if (FullSystem) {
SparcFaultBase::invoke(tc, inst);
- } else {
- doNormalFault(tc, trapType(), false);
+ return;
+ }
- Process *p = tc->getProcessPtr();
+ doNormalFault(tc, trapType(), false);
- //XXX This will only work in faults from a SparcLiveProcess
- SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
- assert(lp);
+ Process *p = tc->getProcessPtr();
- // Then adjust the PC and NPC
- tc->pcState(lp->readFillStart());
- }
+ //XXX This will only work in faults from a SparcLiveProcess
+ SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
+ assert(lp);
+
+ // Then adjust the PC and NPC
+ tc->pcState(lp->readFillStart());
}
void
@@ -704,24 +708,25 @@ TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
{
if (FullSystem) {
SparcFaultBase::invoke(tc, inst);
- } else {
- // In SE, this mechanism is how the process requests a service from
- // the operating system. We'll get the process object from the thread
- // context and let it service the request.
+ return;
+ }
- Process *p = tc->getProcessPtr();
+ // In SE, this mechanism is how the process requests a service from
+ // the operating system. We'll get the process object from the thread
+ // context and let it service the request.
- SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
- assert(lp);
+ Process *p = tc->getProcessPtr();
- lp->handleTrap(_n, tc);
+ SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
+ assert(lp);
- // We need to explicitly advance the pc, since that's not done for us
- // on a faulting instruction
- PCState pc = tc->pcState();
- pc.advance();
- tc->pcState(pc);
- }
+ lp->handleTrap(_n, tc);
+
+ // We need to explicitly advance the pc, since that's not done for us
+ // on a faulting instruction
+ PCState pc = tc->pcState();
+ pc.advance();
+ tc->pcState(pc);
}
} // namespace SparcISA
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index 74b1b2794..272df690c 100644
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -46,21 +46,21 @@ namespace SparcISA {
uint64_t
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
{
- if (FullSystem) {
- const int NumArgumentRegs = 6;
- if (number < NumArgumentRegs) {
- return tc->readIntReg(8 + number);
- } else {
- Addr sp = tc->readIntReg(StackPointerReg);
- FSTranslatingPortProxy* vp = tc->getVirtProxy();
- uint64_t arg = vp->read<uint64_t>(sp + 92 +
- (number-NumArgumentRegs) * sizeof(uint64_t));
- return arg;
- }
- } else {
+ if (!FullSystem) {
panic("getArgument() only implemented for full system\n");
M5_DUMMY_RETURN
}
+
+ const int NumArgumentRegs = 6;
+ if (number < NumArgumentRegs) {
+ return tc->readIntReg(8 + number);
+ } else {
+ Addr sp = tc->readIntReg(StackPointerReg);
+ FSTranslatingPortProxy* vp = tc->getVirtProxy();
+ uint64_t arg = vp->read<uint64_t>(sp + 92 +
+ (number-NumArgumentRegs) * sizeof(uint64_t));
+ return arg;
+ }
}
void
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index e49bbdbac..e95d8e7dc 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -52,43 +52,44 @@ namespace X86ISA
{
void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
{
- if (FullSystem) {
- PCState pcState = tc->pcState();
- Addr pc = pcState.pc();
- DPRINTF(Faults, "RIP %#x: vector %d: %s\n",
- pc, vector, describe());
- using namespace X86ISAInst::RomLabels;
- HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
- MicroPC entry;
- if (m5reg.mode == LongMode) {
- if (isSoft()) {
- entry = extern_label_longModeSoftInterrupt;
- } else {
- entry = extern_label_longModeInterrupt;
- }
+ if (!FullSystem) {
+ FaultBase::invoke(tc, inst);
+ return;
+ }
+
+ PCState pcState = tc->pcState();
+ Addr pc = pcState.pc();
+ DPRINTF(Faults, "RIP %#x: vector %d: %s\n",
+ pc, vector, describe());
+ using namespace X86ISAInst::RomLabels;
+ HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
+ MicroPC entry;
+ if (m5reg.mode == LongMode) {
+ if (isSoft()) {
+ entry = extern_label_longModeSoftInterrupt;
} else {
- entry = extern_label_legacyModeInterrupt;
+ entry = extern_label_longModeInterrupt;
}
- tc->setIntReg(INTREG_MICRO(1), vector);
- tc->setIntReg(INTREG_MICRO(7), pc);
- if (errorCode != (uint64_t)(-1)) {
- if (m5reg.mode == LongMode) {
- entry = extern_label_longModeInterruptWithError;
- } else {
- panic("Legacy mode interrupts with error codes "
- "aren't implementde.\n");
- }
- // Software interrupts shouldn't have error codes. If one
- // does, there would need to be microcode to set it up.
- assert(!isSoft());
- tc->setIntReg(INTREG_MICRO(15), errorCode);
- }
- pcState.upc(romMicroPC(entry));
- pcState.nupc(romMicroPC(entry) + 1);
- tc->pcState(pcState);
} else {
- FaultBase::invoke(tc, inst);
+ entry = extern_label_legacyModeInterrupt;
}
+ tc->setIntReg(INTREG_MICRO(1), vector);
+ tc->setIntReg(INTREG_MICRO(7), pc);
+ if (errorCode != (uint64_t)(-1)) {
+ if (m5reg.mode == LongMode) {
+ entry = extern_label_longModeInterruptWithError;
+ } else {
+ panic("Legacy mode interrupts with error codes "
+ "aren't implementde.\n");
+ }
+ // Software interrupts shouldn't have error codes. If one
+ // does, there would need to be microcode to set it up.
+ assert(!isSoft());
+ tc->setIntReg(INTREG_MICRO(15), errorCode);
+ }
+ pcState.upc(romMicroPC(entry));
+ pcState.nupc(romMicroPC(entry) + 1);
+ tc->pcState(pcState);
}
std::string
@@ -106,12 +107,13 @@ namespace X86ISA
void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
{
X86FaultBase::invoke(tc);
- if (FullSystem) {
- // This is the same as a fault, but it happens -after- the
- // instruction.
- PCState pc = tc->pcState();
- pc.uEnd();
- }
+ if (!FullSystem)
+ return;
+
+ // This is the same as a fault, but it happens -after- the
+ // instruction.
+ PCState pc = tc->pcState();
+ pc.uEnd();
}
void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-25 11:07:12 +0000