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-rw-r--r--src/arch/alpha/regfile.cc6
-rw-r--r--src/arch/alpha/regfile.hh6
-rw-r--r--[-rwxr-xr-x]src/arch/mips/regfile/misc_regfile.cc10
-rw-r--r--src/arch/mips/regfile/regfile.cc5
-rw-r--r--src/arch/mips/regfile/regfile.hh8
-rw-r--r--src/arch/sparc/miscregfile.cc13
-rw-r--r--src/arch/sparc/miscregfile.hh5
-rw-r--r--src/arch/sparc/regfile.cc10
-rw-r--r--src/arch/sparc/regfile.hh5
-rw-r--r--src/arch/sparc/ua2005.cc30
-rw-r--r--src/arch/x86/miscregfile.hh6
-rw-r--r--src/arch/x86/regfile.cc6
-rw-r--r--src/arch/x86/regfile.hh6
13 files changed, 66 insertions, 50 deletions
diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc
index cd648844f..b3aa55b19 100644
--- a/src/arch/alpha/regfile.cc
+++ b/src/arch/alpha/regfile.cc
@@ -33,10 +33,12 @@
#include "arch/alpha/regfile.hh"
#include "cpu/thread_context.hh"
+using namespace std;
+
namespace AlphaISA {
void
-RegFile::serialize(std::ostream &os)
+RegFile::serialize(EventManager *em, ostream &os)
{
intRegFile.serialize(os);
floatRegFile.serialize(os);
@@ -49,7 +51,7 @@ RegFile::serialize(std::ostream &os)
}
void
-RegFile::unserialize(Checkpoint *cp, const std::string &section)
+RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
{
intRegFile.unserialize(cp, section);
floatRegFile.unserialize(cp, section);
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index c9fa8a91b..d6d2f587e 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -43,6 +43,7 @@
//XXX These should be implemented by someone who knows the alpha stuff better
class Checkpoint;
+class EventManager;
class ThreadContext;
namespace AlphaISA {
@@ -202,8 +203,9 @@ class RegFile {
intRegFile.setReg(intReg, val);
}
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string &section);
+ void serialize(EventManager *em, std::ostream &os);
+ void unserialize(EventManager *em, Checkpoint *cp,
+ const std::string &section);
void
changeContext(RegContextParam param, RegContextVal val)
diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc
index 06523a8c9..08487db90 100755..100644
--- a/src/arch/mips/regfile/misc_regfile.cc
+++ b/src/arch/mips/regfile/misc_regfile.cc
@@ -567,7 +567,7 @@ MiscRegFile::scheduleCP0Update(int delay)
//schedule UPDATE
CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
- cp0_event->schedule(curTick + cpu->ticks(delay));
+ cpu->schedule(cp0_event, curTick + cpu->ticks(delay));
}
}
@@ -601,8 +601,7 @@ MiscRegFile::updateCPU()
}
MiscRegFile::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type)
- : Event(&mainEventQueue, CPU_Tick_Pri), cp0(_cp0), cpu(_cpu),
- cp0EventType(e_type)
+ : Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type)
{ }
void
@@ -627,10 +626,7 @@ MiscRegFile::CP0Event::description() const
void
MiscRegFile::CP0Event::scheduleEvent(int delay)
{
- if (squashed())
- reschedule(curTick + cpu->ticks(delay));
- else if (!scheduled())
- schedule(curTick + cpu->ticks(delay));
+ cpu->reschedule(this, curTick + cpu->ticks(delay), true);
}
void
diff --git a/src/arch/mips/regfile/regfile.cc b/src/arch/mips/regfile/regfile.cc
index 996c14f14..a1c8eab6a 100644
--- a/src/arch/mips/regfile/regfile.cc
+++ b/src/arch/mips/regfile/regfile.cc
@@ -193,7 +193,7 @@ RegFile::setNextNPC(Addr val)
}
void
-RegFile::serialize(std::ostream &os)
+RegFile::serialize(EventManager *em, std::ostream &os)
{
intRegFile.serialize(os);
//SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
@@ -207,7 +207,8 @@ RegFile::serialize(std::ostream &os)
}
void
-RegFile::unserialize(Checkpoint *cp, const std::string &section)
+RegFile::unserialize(EventManager *em, Checkpoint *cp,
+ const std::string &section)
{
intRegFile.unserialize(cp, section);
//UNSERIALIZE_ARRAY(floatRegFile);
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index 407d9b50a..076cf45f5 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -41,8 +41,9 @@
//#include "cpu/base.hh"
#include "sim/faults.hh"
-class Checkpoint;
class BaseCPU;
+class Checkpoint;
+class EventManager;
namespace MipsISA
{
@@ -99,8 +100,9 @@ namespace MipsISA
Addr readNextNPC();
void setNextNPC(Addr val);
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string &section);
+ void serialize(EventManager *em, std::ostream &os);
+ void unserialize(EventManager *em, Checkpoint *cp,
+ const std::string &section);
void changeContext(RegContextParam param, RegContextVal val)
{
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index 195db90a6..d66cefa7a 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -593,7 +593,8 @@ void MiscRegFile::setReg(int miscReg,
setRegNoEffect(miscReg, new_val);
}
-void MiscRegFile::serialize(std::ostream & os)
+void
+MiscRegFile::serialize(EventManager *em, std::ostream &os)
{
SERIALIZE_SCALAR(asi);
SERIALIZE_SCALAR(tick);
@@ -670,7 +671,9 @@ void MiscRegFile::serialize(std::ostream & os)
#endif
}
-void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
+void
+MiscRegFile::unserialize(EventManager *em, Checkpoint *cp,
+ const string &section)
{
UNSERIALIZE_SCALAR(asi);
UNSERIALIZE_SCALAR(tick);
@@ -729,15 +732,15 @@ void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
if (tick_cmp) {
tickCompare = new TickCompareEvent(this, tc);
- tickCompare->schedule(tick_cmp);
+ em->schedule(tickCompare, tick_cmp);
}
if (stick_cmp) {
sTickCompare = new STickCompareEvent(this, tc);
- sTickCompare->schedule(stick_cmp);
+ em->schedule(sTickCompare, stick_cmp);
}
if (hstick_cmp) {
hSTickCompare = new HSTickCompareEvent(this, tc);
- hSTickCompare->schedule(hstick_cmp);
+ em->schedule(hSTickCompare, hstick_cmp);
}
}
}
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index bf9c880fa..6a010f529 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -288,9 +288,10 @@ namespace SparcISA
return priContext | (uint32_t)partId << 13;
}
- void serialize(std::ostream & os);
+ void serialize(EventManager *em, std::ostream & os);
- void unserialize(Checkpoint * cp, const std::string & section);
+ void unserialize(EventManager *em, Checkpoint *cp,
+ const std::string & section);
void copyMiscRegs(ThreadContext * tc);
diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc
index 76516daca..8815b094c 100644
--- a/src/arch/sparc/regfile.cc
+++ b/src/arch/sparc/regfile.cc
@@ -219,21 +219,23 @@ int SparcISA::flattenIntIndex(ThreadContext * tc, int reg)
//return intRegFile.flattenIndex(reg);
}
-void RegFile::serialize(std::ostream &os)
+void
+RegFile::serialize(EventManager *em, ostream &os)
{
intRegFile.serialize(os);
floatRegFile.serialize(os);
- miscRegFile.serialize(os);
+ miscRegFile.serialize(em, os);
SERIALIZE_SCALAR(pc);
SERIALIZE_SCALAR(npc);
SERIALIZE_SCALAR(nnpc);
}
-void RegFile::unserialize(Checkpoint *cp, const std::string &section)
+void
+RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
{
intRegFile.unserialize(cp, section);
floatRegFile.unserialize(cp, section);
- miscRegFile.unserialize(cp, section);
+ miscRegFile.unserialize(em, cp, section);
UNSERIALIZE_SCALAR(pc);
UNSERIALIZE_SCALAR(npc);
UNSERIALIZE_SCALAR(nnpc);
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index 581785714..da7e022e9 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -112,8 +112,9 @@ namespace SparcISA
void setIntReg(int intReg, const IntReg &val);
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string &section);
+ void serialize(EventManager *em, std::ostream &os);
+ void unserialize(EventManager *em, Checkpoint *cp,
+ const std::string &section);
public:
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 990250159..7b8524703 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -84,12 +84,12 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
tickCompare = new TickCompareEvent(this, tc);
setRegNoEffect(miscReg, val);
if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled())
- tickCompare->deschedule();
+ cpu->deschedule(tickCompare);
time = (tick_cmpr & mask(63)) - (tick & mask(63));
if (!(tick_cmpr & ~mask(63)) && time > 0) {
if (tickCompare->scheduled())
- tickCompare->deschedule();
- tickCompare->schedule(time * cpu->ticks(1));
+ cpu->deschedule(tickCompare);
+ cpu->schedule(tickCompare, curTick + time * cpu->ticks(1));
}
panic("writing to TICK compare register %#X\n", val);
break;
@@ -99,13 +99,13 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
sTickCompare = new STickCompareEvent(this, tc);
setRegNoEffect(miscReg, val);
if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
- sTickCompare->deschedule();
+ cpu->deschedule(sTickCompare);
time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
cpu->instCount();
if (!(stick_cmpr & ~mask(63)) && time > 0) {
if (sTickCompare->scheduled())
- sTickCompare->deschedule();
- sTickCompare->schedule(time * cpu->ticks(1) + curTick);
+ cpu->deschedule(sTickCompare);
+ cpu->schedule(sTickCompare, curTick + time * cpu->ticks(1));
}
DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
break;
@@ -169,13 +169,13 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
hSTickCompare = new HSTickCompareEvent(this, tc);
setRegNoEffect(miscReg, val);
if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
- hSTickCompare->deschedule();
+ cpu->deschedule(hSTickCompare);
time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
cpu->instCount();
if (!(hstick_cmpr & ~mask(63)) && time > 0) {
if (hSTickCompare->scheduled())
- hSTickCompare->deschedule();
- hSTickCompare->schedule(curTick + time * cpu->ticks(1));
+ cpu->deschedule(hSTickCompare);
+ cpu->schedule(hSTickCompare, curTick + time * cpu->ticks(1));
}
DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
break;
@@ -296,12 +296,14 @@ MiscRegFile::processTickCompare(ThreadContext *tc)
void
MiscRegFile::processSTickCompare(ThreadContext *tc)
{
+ BaseCPU *cpu = tc->getCpuPtr();
+
// since our microcode instructions take two cycles we need to check if
// we're actually at the correct cycle or we need to wait a little while
// more
int ticks;
ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
- tc->getCpuPtr()->instCount();
+ cpu->instCount();
assert(ticks >= 0 && "stick compare missed interrupt cycle");
if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
@@ -311,12 +313,14 @@ MiscRegFile::processSTickCompare(ThreadContext *tc)
setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
}
} else
- sTickCompare->schedule(ticks * tc->getCpuPtr()->ticks(1) + curTick);
+ cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1));
}
void
MiscRegFile::processHSTickCompare(ThreadContext *tc)
{
+ BaseCPU *cpu = tc->getCpuPtr();
+
// since our microcode instructions take two cycles we need to check if
// we're actually at the correct cycle or we need to wait a little while
// more
@@ -326,7 +330,7 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc)
return;
ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
- tc->getCpuPtr()->instCount();
+ cpu->instCount();
assert(ticks >= 0 && "hstick compare missed interrupt cycle");
if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
@@ -337,6 +341,6 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc)
}
// Need to do something to cause interrupt to happen here !!! @todo
} else
- hSTickCompare->schedule(ticks * tc->getCpuPtr()->ticks(1) + curTick);
+ cpu->schedule(hSTickCompare, curTick + ticks * cpu->ticks(1));
}
diff --git a/src/arch/x86/miscregfile.hh b/src/arch/x86/miscregfile.hh
index 3abe4ec58..21caf3aa1 100644
--- a/src/arch/x86/miscregfile.hh
+++ b/src/arch/x86/miscregfile.hh
@@ -115,10 +115,8 @@ namespace X86ISA
class ApicTimerEvent : public Event
{
public:
- ApicTimerEvent() : Event(&mainEventQueue)
- {}
-
- void process()
+ void
+ process()
{
warn("Local APIC timer event doesn't do anything!\n");
}
diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc
index 3fda345cc..c8ec2a957 100644
--- a/src/arch/x86/regfile.cc
+++ b/src/arch/x86/regfile.cc
@@ -228,7 +228,8 @@ int X86ISA::flattenFloatIndex(ThreadContext * tc, int reg)
return reg;
}
-void RegFile::serialize(std::ostream &os)
+void
+RegFile::serialize(EventManager *em, std::ostream &os)
{
intRegFile.serialize(os);
floatRegFile.serialize(os);
@@ -237,7 +238,8 @@ void RegFile::serialize(std::ostream &os)
SERIALIZE_SCALAR(nextRip);
}
-void RegFile::unserialize(Checkpoint *cp, const std::string &section)
+void
+RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
{
intRegFile.unserialize(cp, section);
floatRegFile.unserialize(cp, section);
diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/regfile.hh
index 650181aca..3c2387346 100644
--- a/src/arch/x86/regfile.hh
+++ b/src/arch/x86/regfile.hh
@@ -68,6 +68,7 @@
#include <string>
class Checkpoint;
+class EventManager;
namespace X86ISA
{
@@ -139,8 +140,9 @@ namespace X86ISA
void setIntReg(int intReg, const IntReg &val);
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string &section);
+ void serialize(EventManager *em, std::ostream &os);
+ void unserialize(EventManager *em, Checkpoint *cp,
+ const std::string &section);
public:
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 15:01:39 +0000