diff options
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/sparc/isa/decoder.isa | 14 | ||||
-rw-r--r-- | src/arch/sparc/isa/formats/priv.isa | 14 | ||||
-rw-r--r-- | src/arch/sparc/regfile.hh | 6 |
3 files changed, 20 insertions, 14 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index fa8832920..788e455d8 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -325,12 +325,12 @@ decode OP default Unknown::unknown() 0x28: rdasr({{ Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault); }}); - 0x29: rdhpr({{ + 0x29: HPriv::rdhpr({{ // XXX Need to protect with format that traps non-priv/priv // access Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault); }}); - 0x2A: rdpr({{ + 0x2A: Priv::rdpr({{ // XXX Need to protect with format that traps non-priv // access Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault); @@ -397,15 +397,15 @@ decode OP default Unknown::unknown() 0x0: BasicOperate::saved({{/*Boogy Boogy*/}}); 0x1: BasicOperate::restored({{/*Boogy Boogy*/}}); } - 0x32: wrpr({{ + 0x32: Priv::wrpr({{ // XXX Need to protect with format that traps non-priv // access - xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13); + fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13); }}); - 0x33: wrhpr({{ + 0x33: HPriv::wrhpr({{ // XXX Need to protect with format that traps non-priv/priv // access - xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13); + fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13); }}); 0x34: Trap::fpop1({{fault = new FpDisabled;}}); 0x35: Trap::fpop2({{fault = new FpDisabled;}}); @@ -549,7 +549,7 @@ decode OP default Unknown::unknown() NNPC = Tnpc + 4; Tl = Tl - 1; }}); - 0x1: BasicOperate::retry({{ + 0x1: Priv::retry({{ if(Tl == 0) return new IllegalInstruction; Cwp = Tstate<4:0>; diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa index 7df59d736..28849e621 100644 --- a/src/arch/sparc/isa/formats/priv.isa +++ b/src/arch/sparc/isa/formats/priv.isa @@ -87,9 +87,10 @@ def template PrivExecute {{ if(%(check)s) return new PrivilegedAction; + Fault fault = NoFault; %(code)s; %(op_wb)s; - return NoFault; + return fault; } }}; @@ -116,10 +117,17 @@ let {{ // Primary format for integer operate instructions: def format Priv(code, *opt_flags) {{ - checkCode = "((xc->readMiscReg(PrStart + MISCREG_PSTATE))<2:2>)" + checkCode = '''((xc->readMiscReg(PrStart + MISCREG_PSTATE))<2:2>) || + ((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)''' (header_output, decoder_output, exec_output, decode_block) = doPrivFormat(code, - checkCode, name, Name, opt_flags) + checkCode, name, Name, opt_flags + ('IprAccessOp',)) }}; +def format HPriv(code, *opt_flags) {{ + checkCode = "((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)" + (header_output, decoder_output, + exec_output, decode_block) = doPrivFormat(code, + checkCode, name, Name, opt_flags + ('IprAccessOp',)) +}}; diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index cbeb3c7b9..e5192d684 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -55,14 +55,12 @@ namespace SparcISA // NWINDOWS - number of register windows, can be 3 to 32 const int NWindows = 32; - const int AsrStart = 0; const int PrStart = 32; const int HprStart = 64; const int MiscStart = 96; const uint64_t Bit64 = (1ULL << 63); - class IntRegFile { protected: @@ -625,11 +623,9 @@ namespace SparcISA hpstateFields.red = 1; hpstateFields.hpriv = 1; hpstateFields.tlz = 0; // this is a guess - hintp = 0; // no interrupts pending hstick_cmprFields.int_dis = 1; // disable timer compare interrupts hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing - #else /* //This sets up the initial state of the processor for usermode processes pstateFields.priv = 0; //Process runs in user mode @@ -687,6 +683,8 @@ namespace SparcISA void copyMiscRegs(ThreadContext * tc); + protected: + bool isHyperPriv() { return hpstateFields.hpriv; } bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; } bool isNonPriv() { return !isPriv(); } |