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-rw-r--r--src/arch/alpha/ev5.hh4
-rw-r--r--src/arch/alpha/pagetable.hh4
-rw-r--r--src/arch/alpha/utility.hh4
-rwxr-xr-xsrc/arch/mips/dsp.cc4
-rw-r--r--src/arch/mips/isa/decoder.isa26
-rwxr-xr-xsrc/arch/mips/pagetable.hh4
-rw-r--r--src/arch/mips/utility.cc2
-rw-r--r--src/arch/sparc/faults.cc2
-rw-r--r--src/arch/sparc/isa/formats/mem/util.isa9
-rw-r--r--src/arch/sparc/tlb.cc8
-rw-r--r--src/arch/x86/emulenv.cc2
-rw-r--r--src/arch/x86/insts/microop.cc4
-rw-r--r--src/arch/x86/predecoder.cc8
-rw-r--r--src/arch/x86/regfile.cc2
14 files changed, 42 insertions, 41 deletions
diff --git a/src/arch/alpha/ev5.hh b/src/arch/alpha/ev5.hh
index 4c4f282f1..1915d822b 100644
--- a/src/arch/alpha/ev5.hh
+++ b/src/arch/alpha/ev5.hh
@@ -80,7 +80,7 @@ Phys2K0Seg(Addr addr)
inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
inline Addr DTB_PTE_PPN(uint64_t reg)
-{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
+{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
@@ -90,7 +90,7 @@ inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
inline Addr ITB_PTE_PPN(uint64_t reg)
-{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
+{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
diff --git a/src/arch/alpha/pagetable.hh b/src/arch/alpha/pagetable.hh
index 4f7beb19b..6cf11be56 100644
--- a/src/arch/alpha/pagetable.hh
+++ b/src/arch/alpha/pagetable.hh
@@ -57,9 +57,9 @@ struct VAddr
Addr level3() const
{ return PteAddr(addr >> PageShift); }
Addr level2() const
- { return PteAddr(addr >> NPtePageShift + PageShift); }
+ { return PteAddr(addr >> (NPtePageShift + PageShift)); }
Addr level1() const
- { return PteAddr(addr >> 2 * NPtePageShift + PageShift); }
+ { return PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
};
struct PageTableEntry
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index 84f7cc487..76c6c5726 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -53,14 +53,14 @@ inline bool
isCallerSaveIntegerRegister(unsigned int reg)
{
panic("register classification not implemented");
- return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
+ return (reg >= 1 && reg <= 8) || (reg >= 22 && reg <= 25) || reg == 27;
}
inline bool
isCalleeSaveIntegerRegister(unsigned int reg)
{
panic("register classification not implemented");
- return (reg >= 9 && reg <= 15);
+ return reg >= 9 && reg <= 15;
}
inline bool
diff --git a/src/arch/mips/dsp.cc b/src/arch/mips/dsp.cc
index fc3ae65d6..6e4f7afea 100755
--- a/src/arch/mips/dsp.cc
+++ b/src/arch/mips/dsp.cc
@@ -923,10 +923,10 @@ MipsISA::dspPrecrqu(int32_t a, int32_t b, uint32_t *dspctl)
for (int i = 0; i<2; i++) {
r_values[i] =
- dspSaturate((int64_t)b_values[i] >> SIMD_NBITS[SIMD_FMT_QB] - 1,
+ dspSaturate((int64_t)b_values[i] >> (SIMD_NBITS[SIMD_FMT_QB] - 1),
SIMD_FMT_QB, UNSIGNED, &ouflag);
r_values[i + 2] =
- dspSaturate((int64_t)a_values[i] >> SIMD_NBITS[SIMD_FMT_QB] - 1,
+ dspSaturate((int64_t)a_values[i] >> (SIMD_NBITS[SIMD_FMT_QB] - 1),
SIMD_FMT_QB, UNSIGNED, &ouflag);
}
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index b1cd03ca1..0a12c4f6e 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -416,16 +416,16 @@ decode OPCODE_HI default Unknown::unknown() {
Ctrl_Base_DepTag);
break;
case 25:
- data = 0 | fcsr_val & 0xFE000000 >> 24
- | fcsr_val & 0x00800000 >> 23;
+ data = (fcsr_val & 0xFE000000 >> 24)
+ | (fcsr_val & 0x00800000 >> 23);
break;
case 26:
- data = 0 | fcsr_val & 0x0003F07C;
+ data = fcsr_val & 0x0003F07C;
break;
case 28:
- data = 0 | fcsr_val & 0x00000F80
- | fcsr_val & 0x01000000 >> 21
- | fcsr_val & 0x00000003;
+ data = (fcsr_val & 0x00000F80)
+ | (fcsr_val & 0x01000000 >> 21)
+ | (fcsr_val & 0x00000003);
break;
case 31:
data = fcsr_val;
@@ -1963,7 +1963,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode OP_LO {
format IntOp {
0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }});
- 0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw,RD-1,0) << 32-RD); }});
+ 0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw, RD - 1, 0) << (32 - RD)); }});
}
}
0x2: decode OP_LO {
@@ -2050,11 +2050,11 @@ decode OPCODE_HI default Unknown::unknown() {
format LoadUnalignedMemory {
0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset);
Rt.uw = mem_word << mem_shift |
- Rt.uw & mask(mem_shift);
+ (Rt.uw & mask(mem_shift));
}});
0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset;
- Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) |
- mem_word >> mem_shift;
+ Rt.uw = (Rt.uw & (mask(mem_shift) << (32 - mem_shift))) |
+ (mem_word >> mem_shift);
}});
}
}
@@ -2069,12 +2069,12 @@ decode OPCODE_HI default Unknown::unknown() {
format StoreUnalignedMemory {
0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset);
uint32_t mem_shift = 32 - reg_shift;
- mem_word = mem_word & (mask(reg_shift) << mem_shift) |
- Rt.uw >> reg_shift;
+ mem_word = (mem_word & (mask(reg_shift) << mem_shift)) |
+ (Rt.uw >> reg_shift);
}});
0x6: swr({{ uint32_t reg_shift = 8 * byte_offset;
mem_word = Rt.uw << reg_shift |
- mem_word & (mask(reg_shift));
+ (mem_word & (mask(reg_shift)));
}});
}
format CP0Control {
diff --git a/src/arch/mips/pagetable.hh b/src/arch/mips/pagetable.hh
index 8c43a7b0c..bbed94194 100755
--- a/src/arch/mips/pagetable.hh
+++ b/src/arch/mips/pagetable.hh
@@ -59,9 +59,9 @@ namespace MipsISA {
Addr level3() const
{ return MipsISA::PteAddr(addr >> PageShift); }
Addr level2() const
- { return MipsISA::PteAddr(addr >> NPtePageShift + PageShift); }
+ { return MipsISA::PteAddr(addr >> (NPtePageShift + PageShift)); }
Addr level1() const
- { return MipsISA::PteAddr(addr >> 2 * NPtePageShift + PageShift); }
+ { return MipsISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
};
// ITB/DTB page table entry
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 36cf76c67..1985c0f43 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -145,7 +145,7 @@ genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
{
int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
- fcsr = bits(fcsr, 31, cc_idx + 1) << cc_idx + 1 |
+ fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) |
cc_val << cc_idx |
bits(fcsr, cc_idx - 1, 0);
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index e201cef95..9c189d164 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -546,7 +546,7 @@ void SparcFaultBase::invoke(ThreadContext * tc)
doNormalFault(tc, trapType(), true);
getHyperVector(tc, PC, NPC, 2);
} else if (level == Hyperprivileged ||
- level == Privileged && trapType() >= 384) {
+ (level == Privileged && trapType() >= 384)) {
doNormalFault(tc, trapType(), true);
getHyperVector(tc, PC, NPC, trapType());
} else {
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 38cde9a50..f2a2327ee 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -314,10 +314,11 @@ let {{
# are split into ones that are available in priv and hpriv, and
# those that are only available in hpriv
AlternateASIPrivFaultCheck = '''
- if(!bits(Pstate,2,2) && !bits(Hpstate,2,2) && !AsiIsUnPriv((ASI)EXT_ASI) ||
- !bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI))
- fault = new PrivilegedAction;
- else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
+ if ((!bits(Pstate,2,2) && !bits(Hpstate,2,2) &&
+ !AsiIsUnPriv((ASI)EXT_ASI)) ||
+ (!bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI)))
+ fault = new PrivilegedAction;
+ else if (AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
fault = new PrivilegedAction;
'''
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index defa33c51..125ceba69 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -562,7 +562,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
asi = (ASI)req->getAsi();
bool implicit = false;
bool hpriv = bits(tlbdata,0,0);
- bool unaligned = (vaddr & size-1);
+ bool unaligned = vaddr & (size - 1);
DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
vaddr, size, asi);
@@ -801,8 +801,8 @@ handleIntRegAccess:
return new PrivilegedAction;
}
- if (asi == ASI_SWVR_UDB_INTR_W && !write ||
- asi == ASI_SWVR_UDB_INTR_R && write) {
+ if ((asi == ASI_SWVR_UDB_INTR_W && !write) ||
+ (asi == ASI_SWVR_UDB_INTR_R && write)) {
writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
return new DataAccessException;
}
@@ -822,7 +822,7 @@ handleQueueRegAccess:
writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
return new PrivilegedAction;
}
- if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
+ if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) {
writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
return new DataAccessException;
}
diff --git a/src/arch/x86/emulenv.cc b/src/arch/x86/emulenv.cc
index 31b705d79..142e233db 100644
--- a/src/arch/x86/emulenv.cc
+++ b/src/arch/x86/emulenv.cc
@@ -91,7 +91,7 @@ void EmulEnv::doModRM(const ExtMachInst & machInst)
//Figure out what segment to use. This won't be entirely accurate since
//the presence of a displacement is supposed to make the instruction
//default to the data segment.
- if (base != INTREG_RBP && base != INTREG_RSP ||
+ if ((base != INTREG_RBP && base != INTREG_RSP) ||
0/*Has an immediate offset*/) {
seg = SEGMENT_REG_DS;
//Handle any segment override that might have been in the instruction
diff --git a/src/arch/x86/insts/microop.cc b/src/arch/x86/insts/microop.cc
index 494c0b303..c7bfc3703 100644
--- a/src/arch/x86/insts/microop.cc
+++ b/src/arch/x86/insts/microop.cc
@@ -98,7 +98,7 @@ namespace X86ISA
case ConditionTests::SxOF:
return ccflags.sf ^ ccflags.of;
case ConditionTests::SxOvZF:
- return ccflags.sf ^ ccflags.of | ccflags.zf;
+ return (ccflags.sf ^ ccflags.of) | ccflags.zf;
case ConditionTests::False:
return false;
case ConditionTests::NotECF:
@@ -131,7 +131,7 @@ namespace X86ISA
case ConditionTests::NotSxOF:
return !(ccflags.sf ^ ccflags.of);
case ConditionTests::NotSxOvZF:
- return !(ccflags.sf ^ ccflags.of | ccflags.zf);
+ return !((ccflags.sf ^ ccflags.of) | ccflags.zf);
}
panic("Unknown condition: %d\n", condition);
return true;
diff --git a/src/arch/x86/predecoder.cc b/src/arch/x86/predecoder.cc
index 1d415ffea..9d60089e3 100644
--- a/src/arch/x86/predecoder.cc
+++ b/src/arch/x86/predecoder.cc
@@ -319,17 +319,17 @@ namespace X86ISA
if (emi.mode.submode != SixtyFourBitMode &&
!csAttr.defaultSize) {
//figure out 16 bit displacement size
- if(modRM.mod == 0 && modRM.rm == 6 || modRM.mod == 2)
+ if ((modRM.mod == 0 && modRM.rm == 6) || modRM.mod == 2)
displacementSize = 2;
- else if(modRM.mod == 1)
+ else if (modRM.mod == 1)
displacementSize = 1;
else
displacementSize = 0;
} else {
//figure out 32/64 bit displacement size
- if(modRM.mod == 0 && modRM.rm == 5 || modRM.mod == 2)
+ if ((modRM.mod == 0 && modRM.rm == 5) || modRM.mod == 2)
displacementSize = 4;
- else if(modRM.mod == 1)
+ else if (modRM.mod == 1)
displacementSize = 1;
else
displacementSize = 0;
diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc
index c27ab08ba..3fda345cc 100644
--- a/src/arch/x86/regfile.cc
+++ b/src/arch/x86/regfile.cc
@@ -214,7 +214,7 @@ int X86ISA::flattenIntIndex(ThreadContext * tc, int reg)
//If we need to fold over the index to match byte semantics, do that.
//Otherwise, just strip off any extra bits and pass it through.
if (reg & (1 << 6))
- return (reg & ~(1 << 6) - 0x4);
+ return (reg & (~(1 << 6) - 0x4));
else
return (reg & ~(1 << 6));
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-11 08:07:45 +0000