diff options
Diffstat (limited to 'src/arch')
| -rwxr-xr-x | src/arch/isa_parser.py | 9 | ||||
| -rw-r--r-- | src/arch/sparc/isa/decoder.isa | 10 | ||||
| -rw-r--r-- | src/arch/sparc/isa/operands.isa | 3 |
3 files changed, 12 insertions, 10 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 39500df36..9b63c8842 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1124,9 +1124,12 @@ def buildOperandTypeMap(userDict, lineno): ctype = 'float' elif size == 64: ctype = 'double' - elif desc == 'twin int': + elif desc == 'twin64 int': is_signed = 0 ctype = 'Twin64_t' + elif desc == 'twin32 int': + is_signed = 0 + ctype = 'Twin32_t' if ctype == '': error(lineno, 'Unrecognized type description "%s" in userDict') operandTypeMap[ext] = (size, ctype, is_signed) @@ -1159,7 +1162,7 @@ class Operand(object): # template must be careful not to use it if it doesn't apply. if self.isMem(): self.mem_acc_size = self.makeAccSize() - if self.ctype == 'Twin64_t': + if self.ctype in ['Twin32_t', 'Twin64_t']: self.mem_acc_type = 'Twin' else: self.mem_acc_type = 'uint' @@ -1392,7 +1395,7 @@ class MemOperand(Operand): # Note that initializations in the declarations are solely # to avoid 'uninitialized variable' errors from the compiler. # Declare memory data variable. - if self.ctype == 'Twin64_t': + if self.ctype in ['Twin32_t','Twin64_t']: return "%s %s; %s.a = 0; %s.b = 0;\n" % (self.ctype, self.base_name, self.base_name, self.base_name) c = '%s %s = 0;\n' % (self.ctype, self.base_name) diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 36b9d1caa..2e85e1274 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1160,9 +1160,8 @@ decode OP default Unknown::unknown() 0x01: ldub({{Rd = Mem.ub;}}); 0x02: lduh({{Rd = Mem.uhw;}}); 0x03: ldtw({{ - uint64_t val = Mem.udw; - RdLow = val<31:0>; - RdHigh = val<63:32>; + RdLow = (Mem.tuw).a; + RdHigh = (Mem.tuw).b; }}); } format Store { @@ -1250,9 +1249,8 @@ decode OP default Unknown::unknown() {{RdLow.udw = (Mem.tudw).a; RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); default: ldtwa({{ - uint64_t val = Mem.udw; - RdLow = val<31:0>; - RdHigh = val<63:32>; + RdLow = (Mem.tuw).a; + RdHigh = (Mem.tuw).b; }}, {{EXT_ASI}}); } } diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 092544aab..038919bd1 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -37,7 +37,8 @@ def operand_types {{ 'uw' : ('unsigned int', 32), 'sdw' : ('signed int', 64), 'udw' : ('unsigned int', 64), - 'tudw' : ('twin int', 64), + 'tudw' : ('twin64 int', 64), + 'tuw' : ('twin32 int', 32), 'sf' : ('float', 32), 'df' : ('float', 64), 'qf' : ('float', 128) |