diff options
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/tlb.cc | 16 | ||||
| -rw-r--r-- | src/arch/arm/tlb.hh | 1 | ||||
| -rw-r--r-- | src/arch/generic/memhelpers.hh | 1 | ||||
| -rw-r--r-- | src/arch/x86/tlb.cc | 14 | ||||
| -rw-r--r-- | src/arch/x86/tlb.hh | 1 |
5 files changed, 33 insertions, 0 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 79eef1b8d..521a43226 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -536,6 +536,11 @@ TLB::regStats() .name(name() + ".prefetch_faults") .desc("Number of TLB faults due to prefetch") ; + + specTLBMisses + .name(name() + ".spec_tlb_misses") + .desc("Number of TLB misses from a speculative mem instructions") + ; domainFaults .name(name() + ".domain_faults") @@ -1426,6 +1431,17 @@ TLB::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, vaddr_tainted, ArmFault::PrefetchTLBMiss, isStage2); } + if (req->isSpec()) { + // if the request is a prefetch don't attempt to fill the TLB or go + // any further with the memory access (here we can safely use the + // fault status for the short desc. format in all cases) + specTLBMisses++; + //FIXME: currently resue the prefetch tlbmiss fault + //do not want to introduce new fault declaration + return std::make_shared<PrefetchAbort>( + vaddr_tainted, ArmFault::PrefetchTLBMiss, isStage2); + } + if (is_fetch) instMisses++; else if (is_write) diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 336b31b78..9f2acda6c 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -177,6 +177,7 @@ class TLB : public BaseTLB mutable Stats::Scalar flushedEntries; mutable Stats::Scalar alignFaults; mutable Stats::Scalar prefetchFaults; + mutable Stats::Scalar specTLBMisses; mutable Stats::Scalar domainFaults; mutable Stats::Scalar permsFaults; diff --git a/src/arch/generic/memhelpers.hh b/src/arch/generic/memhelpers.hh index 6fe1707a0..c77612d34 100644 --- a/src/arch/generic/memhelpers.hh +++ b/src/arch/generic/memhelpers.hh @@ -53,6 +53,7 @@ /// Initiate a read from memory in timing mode. Note that the 'mem' /// parameter is unused; only the type of that parameter is used /// to determine the size of the access. +// XC: executeContextPtr [mengjia] template <class XC, class MemT> Fault initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr, diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 8e83208f4..ba14d7ef3 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -340,6 +340,17 @@ TLB::translate(const RequestPtr &req, wrAccesses++; } if (!entry) { + if(req->isSpec()){ + // [InvisiSpec] do not perform TLB fill for + // speculative load + specMisses++; + DPRINTF(TLB, "Get a TLB miss for a speculative load " + "address %#x at pc %#x.\n", + vaddr, tc->instAddr()); + //FIXME: currently reuse the GeneralProtection fault + //instead of creating new faults + return std::make_shared<GeneralProtection>(0); + } DPRINTF(TLB, "Handling a TLB miss for " "address %#x at pc %#x.\n", vaddr, tc->instAddr()); @@ -472,6 +483,9 @@ TLB::regStats() .name(name() + ".wrMisses") .desc("TLB misses on write requests"); + specMisses + .name(name() + ".spec_tlb_misses") + .desc("TLB misses on speculative memory requests"); } void diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index 827ab8166..7213b8b41 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -105,6 +105,7 @@ namespace X86ISA Stats::Scalar wrAccesses; Stats::Scalar rdMisses; Stats::Scalar wrMisses; + Stats::Scalar specMisses; Fault translateInt(const RequestPtr &req, ThreadContext *tc); |