4 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index 04bac3996..ca20cf585 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -75,3 +75,5 @@ if env['TARGET_ISA'] == 'alpha':
     for f in isa_desc_files:
         if not f.path.endswith('.hh'):
             Source(f)
+
+    TraceFlag('Context')
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index e1d2146eb..f4be39eca 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -43,6 +43,8 @@ if env['TARGET_ISA'] == 'mips':
 
     SimObject('MipsTLB.py')
 
+    TraceFlag('MipsPRA')
+
     if env['FULL_SYSTEM']:
         #Insert Full-System Files Here
         pass
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index 81e96a8d6..a86c00250 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -44,6 +44,7 @@ if env['TARGET_ISA'] == 'sparc':
     Source('utility.cc')
 
     SimObject('SparcTLB.py')
+    TraceFlag('Sparc')
 
     if env['FULL_SYSTEM']:
         SimObject('SparcSystem.py')
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 3a94866bb..68a18d4c0 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -105,6 +105,8 @@ if env['TARGET_ISA'] == 'x86':
     Source('utility.cc')
 
     SimObject('X86TLB.py')
+    TraceFlag('Predecoder')
+    TraceFlag('X86')
 
     if env['FULL_SYSTEM']:
         SimObject('X86System.py')