diff options
Diffstat (limited to 'src/arch')
| -rwxr-xr-x | src/arch/isa_parser.py | 4 | ||||
| -rw-r--r-- | src/arch/sparc/miscregfile.cc | 4 | ||||
| -rw-r--r-- | src/arch/sparc/miscregfile.hh | 5 | ||||
| -rw-r--r-- | src/arch/sparc/ua2005.cc | 5 |
4 files changed, 8 insertions, 10 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 9b63c8842..21860a2e1 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1368,7 +1368,7 @@ class ControlRegOperand(Operand): bit_select = 0 if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to read control register as FP') - base = 'xc->readMiscRegOperandWithEffect(this, %s)' % self.src_reg_idx + base = 'xc->readMiscRegOperand(this, %s)' % self.src_reg_idx if self.size == self.dflt_size: return '%s = %s;\n' % (self.base_name, base) else: @@ -1378,7 +1378,7 @@ class ControlRegOperand(Operand): def makeWrite(self): if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to write control register as FP') - wb = 'xc->setMiscRegOperandWithEffect(this, %s, %s);\n' % \ + wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \ (self.dest_reg_idx, self.base_name) wb += 'if (traceData) { traceData->setData(%s); }' % \ self.base_name diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index e7b866e6f..20bc4ae5d 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -374,7 +374,7 @@ MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc) case MISCREG_QUEUE_NRES_ERROR_TAIL: #if FULL_SYSTEM case MISCREG_HPSTATE: - return readFSRegWithEffect(miscReg, tc); + return readFSReg(miscReg, tc); #else case MISCREG_HPSTATE: //HPSTATE is special because because sometimes in privilege checks for instructions @@ -682,7 +682,7 @@ void MiscRegFile::setReg(int miscReg, case MISCREG_QUEUE_NRES_ERROR_TAIL: #if FULL_SYSTEM case MISCREG_HPSTATE: - setFSRegWithEffect(miscReg, val, tc); + setFSReg(miscReg, val, tc); return; #else case MISCREG_HPSTATE: diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index cb46eb2aa..6063c21c8 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -257,9 +257,8 @@ namespace SparcISA // These need to check the int_dis field and if 0 then // set appropriate bit in softint and checkinterrutps on the cpu #if FULL_SYSTEM - void setFSRegWithEffect(int miscReg, const MiscReg &val, - ThreadContext *tc); - MiscReg readFSRegWithEffect(int miscReg, ThreadContext * tc); + void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc); + MiscReg readFSReg(int miscReg, ThreadContext * tc); // Update interrupt state on softint or pil change void checkSoftInt(ThreadContext *tc); diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 7a16dc352..6c8a987fe 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -59,8 +59,7 @@ MiscRegFile::checkSoftInt(ThreadContext *tc) void -MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, - ThreadContext *tc) +MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) { int64_t time; switch (miscReg) { @@ -196,7 +195,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, } MiscReg -MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc) +MiscRegFile::readFSReg(int miscReg, ThreadContext * tc) { switch (miscReg) { /* Privileged registers. */ |