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-rw-r--r--src/arch/x86/insts/microop.cc8
-rw-r--r--src/arch/x86/isa_traits.hh2
2 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/x86/insts/microop.cc b/src/arch/x86/insts/microop.cc
index 4f464927a..35ee9efaa 100644
--- a/src/arch/x86/insts/microop.cc
+++ b/src/arch/x86/insts/microop.cc
@@ -55,7 +55,7 @@ namespace X86ISA
case ConditionTests::EZF:
return ccflags.ezf;
case ConditionTests::SZnZF:
- return !(!ccflags.ezf & ccflags.zf);
+ return !(!ccflags.ezf && ccflags.zf);
case ConditionTests::MSTRZ:
panic("This condition is not implemented!");
case ConditionTests::STRZ:
@@ -63,7 +63,7 @@ namespace X86ISA
case ConditionTests::MSTRC:
panic("This condition is not implemented!");
case ConditionTests::STRZnEZF:
- return !ccflags.ezf & ccflags.zf;
+ return !ccflags.ezf && ccflags.zf;
//And no interrupts or debug traps are waiting
case ConditionTests::OF:
return ccflags.of;
@@ -88,7 +88,7 @@ namespace X86ISA
case ConditionTests::NotEZF:
return !ccflags.ezf;
case ConditionTests::NotSZnZF:
- return !ccflags.ezf & ccflags.zf;
+ return !ccflags.ezf && ccflags.zf;
case ConditionTests::NotMSTRZ:
panic("This condition is not implemented!");
case ConditionTests::NotSTRZ:
@@ -96,7 +96,7 @@ namespace X86ISA
case ConditionTests::NotMSTRC:
panic("This condition is not implemented!");
case ConditionTests::STRnZnEZF:
- return !ccflags.ezf & !ccflags.zf;
+ return !ccflags.ezf && !ccflags.zf;
//And no interrupts or debug traps are waiting
case ConditionTests::NotOF:
return !ccflags.of;
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index f4fdb59e5..6e5373ca1 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -68,7 +68,7 @@ namespace X86ISA
const bool CurThreadInfoImplemented = false;
const int CurThreadInfoReg = -1;
- const ExtMachInst NoopMachInst = {
+ const ExtMachInst NoopMachInst M5_VAR_USED = {
0x0, // No legacy prefixes.
0x0, // No rex prefix.
{ OneByteOpcode, 0x90 }, // One opcode byte, 0x90.