diff options
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/alpha/faults.hh | 2 | ||||
| -rw-r--r-- | src/arch/alpha/utility.hh | 2 | ||||
| -rw-r--r-- | src/arch/arm/faults.hh | 2 | ||||
| -rw-r--r-- | src/arch/arm/utility.cc | 2 | ||||
| -rw-r--r-- | src/arch/mips/faults.hh | 2 | ||||
| -rw-r--r-- | src/arch/mips/isa/decoder.isa | 4 | ||||
| -rw-r--r-- | src/arch/sparc/isa/decoder.isa | 16 |
7 files changed, 15 insertions, 15 deletions
diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh index 005d8af8a..80e3ae5e1 100644 --- a/src/arch/alpha/faults.hh +++ b/src/arch/alpha/faults.hh @@ -40,7 +40,7 @@ namespace AlphaISA { -typedef const Addr FaultVect; +typedef Addr FaultVect; class AlphaFault : public FaultBase { diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index a52125066..45e47b5e8 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -78,7 +78,7 @@ inline void startupCPU(ThreadContext *tc, int cpuId) inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } // User Virtual -inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } +inline bool IsUSeg(Addr a) { assert(USegBase == 0); return a <= USegEnd; } // Kernel Direct Mapped inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index ef87ee145..02d2e81f5 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -58,7 +58,7 @@ namespace ArmISA { -typedef const Addr FaultOffset; +typedef Addr FaultOffset; class ArmFault : public FaultBase { diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index bedd4a0b0..a4ae849c1 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -209,7 +209,7 @@ getMPIDR(ArmSystem *arm_sys, ThreadContext *tc) // We deliberately extend both the Cluster ID and CPU ID fields to allow // for simulation of larger systems assert((0 <= tc->cpuId()) && (tc->cpuId() < 256)); - assert((0 <= tc->socketId()) && (tc->socketId() < 65536)); + assert(tc->socketId() < 65536); if (arm_sys->multiThread) { return 0x80000000 | // multiprocessor extensions available tc->contextId(); diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh index d843acc50..1ec726d17 100644 --- a/src/arch/mips/faults.hh +++ b/src/arch/mips/faults.hh @@ -45,7 +45,7 @@ namespace MipsISA { -typedef const Addr FaultVect; +typedef Addr FaultVect; enum ExcCode { // A dummy value to use when the code isn't defined or doesn't matter. diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index a62dbb7bb..52cbc4041 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -2404,7 +2404,7 @@ decode OPCODE_HI default Unknown::unknown() { 0x3: decode OP_LO { format DspHiLoOp { 0x2: shilo({{ - if (sext<6>(HILOSA) < 0) { + if ((int64_t)sext<6>(HILOSA) < 0) { dspac = (uint64_t)dspac << -sext<6>(HILOSA); } else { @@ -2413,7 +2413,7 @@ decode OPCODE_HI default Unknown::unknown() { } }}); 0x3: shilov({{ - if (sext<6>(Rs_sw<5:0>) < 0) { + if ((int64_t)sext<6>(Rs_sw<5:0>) < 0) { dspac = (uint64_t)dspac << -sext<6>(Rs_sw<5:0>); } else { diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index befac53e6..492e1a00a 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -669,13 +669,13 @@ decode OP default Unknown::unknown() }}); 0x43: FpUnimpl::fmovq_fcc1(); 0x45: fmovrslez({{ - if (Rs1 <= 0) + if ((int64_t)Rs1 <= 0) Frds = Frs2s; else Frds = Frds; }}); 0x46: fmovrdlez({{ - if (Rs1 <= 0) + if ((int64_t)Rs1 <= 0) Frd = Frs2; else Frd = Frd; @@ -740,13 +740,13 @@ decode OP default Unknown::unknown() }}); 0x57: FpUnimpl::fcmpeq(); 0x65: fmovrslz({{ - if (Rs1 < 0) + if ((int64_t)Rs1 < 0) Frds = Frs2s; else Frds = Frds; }}); 0x66: fmovrdlz({{ - if (Rs1 < 0) + if ((int64_t)Rs1 < 0) Frd = Frs2; else Frd = Frd; @@ -792,26 +792,26 @@ decode OP default Unknown::unknown() }}); 0xC3: FpUnimpl::fmovq_fcc3(); 0xC5: fmovrsgz({{ - if (Rs1 > 0) + if ((int64_t)Rs1 > 0) Frds = Frs2s; else Frds = Frds; }}); 0xC6: fmovrdgz({{ - if (Rs1 > 0) + if ((int64_t)Rs1 > 0) Frd = Frs2; else Frd = Frd; }}); 0xC7: FpUnimpl::fmovrqgz(); 0xE5: fmovrsgez({{ - if (Rs1 >= 0) + if ((int64_t)Rs1 >= 0) Frds = Frs2s; else Frds = Frds; }}); 0xE6: fmovrdgez({{ - if (Rs1 >= 0) + if ((int64_t)Rs1 >= 0) Frd = Frs2; else Frd = Frd; |