diff options
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/stage2_mmu.cc | 2 | ||||
| -rw-r--r-- | src/arch/x86/pagetable_walker.hh | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc index 5c28d073e..ba820e339 100644 --- a/src/arch/arm/stage2_mmu.cc +++ b/src/arch/arm/stage2_mmu.cc @@ -51,7 +51,7 @@ using namespace ArmISA; Stage2MMU::Stage2MMU(const Params *p) : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb), port(_stage1Tlb->getTableWalker(), p->sys), - masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker()->name())) + masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker())) { // we use the stage-one table walker as the parent of the port, // and to get our master id, this is done to keep things diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh index d71db7ea3..d5aa631d2 100644 --- a/src/arch/x86/pagetable_walker.hh +++ b/src/arch/x86/pagetable_walker.hh @@ -203,7 +203,7 @@ namespace X86ISA Walker(const Params *params) : MemObject(params), port(name() + ".port", this), funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system), - masterId(sys->getMasterId(name())), + masterId(sys->getMasterId(this)), numSquashable(params->num_squash_per_cycle), startWalkWrapperEvent([this]{ startWalkWrapper(); }, name()) { |