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-rw-r--r--src/arch/arm/insts/misc.hh8
-rw-r--r--src/arch/arm/isa/formats/misc.isa4
-rw-r--r--src/arch/arm/isa/templates/misc.isa8
3 files changed, 10 insertions, 10 deletions
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 4217dc6f1..0c864559e 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -97,13 +97,13 @@ class MsrRegOp : public MsrBase
class MrrcOp : public PredOp
{
protected:
- IntRegIndex op1;
+ MiscRegIndex op1;
IntRegIndex dest;
IntRegIndex dest2;
uint32_t imm;
MrrcOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _op1, IntRegIndex _dest, IntRegIndex _dest2,
+ MiscRegIndex _op1, IntRegIndex _dest, IntRegIndex _dest2,
uint32_t _imm) :
PredOp(mnem, _machInst, __opClass), op1(_op1), dest(_dest),
dest2(_dest2), imm(_imm)
@@ -117,11 +117,11 @@ class McrrOp : public PredOp
protected:
IntRegIndex op1;
IntRegIndex op2;
- IntRegIndex dest;
+ MiscRegIndex dest;
uint32_t imm;
McrrOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _dest,
+ IntRegIndex _op1, IntRegIndex _op2, MiscRegIndex _dest,
uint32_t _imm) :
PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2),
dest(_dest), imm(_imm)
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 7d3865104..925ed55cd 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -274,8 +274,8 @@ let {{
uint32_t iss = mcrrMrrcIssBuild(isRead, crm, rt, rt2, opc1);
if (isRead)
- return new Mrrc15(machInst, (IntRegIndex) miscReg, rt2, rt, iss);
- return new Mcrr15(machInst, rt2, rt, (IntRegIndex) miscReg, iss);
+ return new Mrrc15(machInst, miscReg, rt2, rt, iss);
+ return new Mcrr15(machInst, rt2, rt, miscReg, iss);
} else {
return new FailUnimplemented(isRead ? "mrrc" : "mcrr", machInst,
csprintf("%s %s",
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index 5cd4637a6..d661b4f18 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -183,7 +183,7 @@ class %(class_name)s : public %(base_class)s
protected:
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
+ %(class_name)s(ExtMachInst machInst, MiscRegIndex _op1,
IntRegIndex _dest, IntRegIndex _dest2, uint32_t imm);
%(BasicExecDeclare)s
};
@@ -191,7 +191,7 @@ class %(class_name)s : public %(base_class)s
def template MrrcOpConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex op1,
+ MiscRegIndex op1,
IntRegIndex dest,
IntRegIndex dest2,
uint32_t imm)
@@ -214,7 +214,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2,
- IntRegIndex _dest, uint32_t imm);
+ MiscRegIndex _dest, uint32_t imm);
%(BasicExecDeclare)s
};
}};
@@ -223,7 +223,7 @@ def template McrrOpConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex op1,
IntRegIndex op2,
- IntRegIndex dest,
+ MiscRegIndex dest,
uint32_t imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, op1, op2,
dest, imm)