diff options
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/tlb.cc | 2 | ||||
| -rw-r--r-- | src/arch/sparc/tlb.cc | 2 | ||||
| -rw-r--r-- | src/arch/x86/tlb.cc | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 8cce5c152..febc6d081 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -147,7 +147,7 @@ TLB::checkCacheability(RequestPtr &req) // or by the TLB entry if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) { // mark request as uncacheable - req->setFlags(req->getFlags() | Request::UNCACHEABLE); + req->setFlags(Request::UNCACHEABLE); } return NoFault; } diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 1b84a0784..41b0f2043 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -837,7 +837,7 @@ handleSparcErrorRegAccess: regAccessOk: handleMmuRegAccess: DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); - req->setMmapedIpr(true); + req->setFlags(Request::MMAPED_IPR); req->setPaddr(req->getVaddr()); return NoFault; }; diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 418f6ffb2..5280b9ba8 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -197,7 +197,7 @@ TLB::translateInt(RequestPtr req, ThreadContext *tc) panic("CPUID memory space not yet implemented!\n"); } else if (prefix == IntAddrPrefixMSR) { vaddr = vaddr >> 3; - req->setMmapedIpr(true); + req->setFlags(Request::MMAPED_IPR); Addr regNum = 0; switch (vaddr & ~IntAddrPrefixMask) { case 0x10: @@ -526,7 +526,7 @@ TLB::translateInt(RequestPtr req, ThreadContext *tc) // space. assert(!(IOPort & ~0xFFFF)); if (IOPort == 0xCF8 && req->getSize() == 4) { - req->setMmapedIpr(true); + req->setFlags(Request::MMAPED_IPR); req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); } else if ((IOPort & ~mask(2)) == 0xCFC) { Addr configAddress = |