3 files changed, 16 insertions, 2 deletions
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 98dc1760d..88f2a455f 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -92,8 +92,7 @@ TableWalker::getPort(const std::string &if_name, int idx)
 {
     if (if_name == "port") {
         if (port != NULL)
-            fatal("%s: port already connected to %s",
-                  name(), port->getPeer()->name());
+            return port;
         System *sys = params()->sys;
         Tick minb = params()->min_backoff;
         Tick maxb = params()->max_backoff;
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 6d6da15c8..f142e03f8 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -693,6 +693,18 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
     return fault;
 }
 
+Port*
+TLB::getPort()
+{
+#if FULL_SYSTEM
+    return tableWalker->getPort("port");
+#else
+    return NULL;
+#endif
+}
+
+
+
 ArmISA::TLB *
 ArmTLBParams::create()
 {
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 0b8bc1046..21062ea0d 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -209,6 +209,9 @@ class TLB : public BaseTLB
 
     void regStats();
 
+    // Get the port from the table walker and return it
+    virtual Port *getPort();
+
     // Caching misc register values here.
     // Writing to misc registers needs to invalidate them.
     // translateFunctional/translateSe/translateFs checks if they are