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-rw-r--r--src/arch/arm/isa/decoder/arm.isa4
-rw-r--r--src/arch/arm/isa/formats/mem.isa165
-rw-r--r--src/arch/arm/isa/insts/insts.isa3
-rw-r--r--src/arch/arm/isa/insts/str.isa139
-rw-r--r--src/arch/arm/isa/templates/mem.isa98
5 files changed, 259 insertions, 150 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa
index e493f4455..f5e48f39d 100644
--- a/src/arch/arm/isa/decoder/arm.isa
+++ b/src/arch/arm/isa/decoder/arm.isa
@@ -255,9 +255,9 @@ format DataOp {
}});
}
}
- 0x2: AddrMode2::addrMode2(True, Disp, disp);
+ 0x2: AddrMode2::addrMode2(True);
0x3: decode OPCODE_4 {
- 0: AddrMode2::addrMode2(False, Shift, Rm_Imm);
+ 0: AddrMode2::addrMode2(False);
1: decode MEDIA_OPCODE {
0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions();
0x8: decode MISC_OPCODE {
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
index 5f8a3695a..c25006d57 100644
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -83,137 +83,10 @@ def template LoadStoreConstructor {{
}
}};
-
-def template StoreExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- Addr EA;
- Fault fault = NoFault;
-
- %(op_decl)s;
- %(op_rd)s;
- %(ea_code)s;
-
- if (%(predicate_test)s)
- {
- if (fault == NoFault) {
- %(memacc_code)s;
- }
-
- if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, NULL);
- }
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
- }
-
- return fault;
- }
-}};
-
-def template StoreInitiateAcc {{
- Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- Addr EA;
- Fault fault = NoFault;
-
- %(op_decl)s;
- %(op_rd)s;
- %(ea_code)s;
-
- if (%(predicate_test)s)
- {
- if (fault == NoFault) {
- %(memacc_code)s;
- }
-
- if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, NULL);
- }
-
- // Need to write back any potential address register update
- if (fault == NoFault) {
- %(op_wb)s;
- }
- }
-
- return fault;
- }
-}};
-
-
-def template StoreCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt,
- %(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- Fault fault = NoFault;
-
- %(op_decl)s;
- %(op_rd)s;
-
- if (%(predicate_test)s)
- {
- if (fault == NoFault) {
- %(op_wb)s;
- }
- }
-
- return fault;
- }
-}};
-
-def template StoreCondCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt,
- %(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- Fault fault = NoFault;
-
- %(op_dest_decl)s;
-
- if (%(predicate_test)s)
- {
- if (fault == NoFault) {
- %(op_wb)s;
- }
- }
-
- return fault;
- }
-}};
-
let {{
def buildPUBWLCase(p, u, b, w, l):
return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0)
- def buildMode2Inst(p, u, b, w, l, suffix, offset):
- mnem = ("str", "ldr")[l]
- op = ("-", "+")[u]
- offset = op + ArmGenericCodeSubs(offset);
- mem = ("Mem", "Mem.ub")[b]
- code = ("%s = Rd;", "Rd = %s;")[l] % mem
- ea_code = "EA = Rn %s;" % ("", offset)[p]
- if p == 0 or w == 1:
- code += "Rn = Rn %s;" % offset
- if p == 0 and w == 0:
- # Here's where we'll tack on a flag to make this a usermode access.
- mnem += "t"
- type = ("Store", "Load")[l]
- newSuffix = "_%s_P%dU%dB%dW%d" % (suffix, p, u, b, w)
- if b == 1:
- mnem += "b"
- return LoadStoreBase(mnem, mnem.capitalize() + newSuffix,
- ea_code, code, mem_flags = [], inst_flags = [],
- base_class = 'Memory' + suffix,
- exec_template_base = type.capitalize())
-
def buildMode3Inst(p, u, i, w, type, code, mnem):
op = ("-", "+")[u]
offset = ("%s Rm", "%s hilo")[i] % op
@@ -228,7 +101,7 @@ let {{
exec_template_base = type.capitalize())
}};
-def format AddrMode2(imm, suffix, offset) {{
+def format AddrMode2(imm) {{
if eval(imm):
imm = True
else:
@@ -243,20 +116,6 @@ def format AddrMode2(imm, suffix, offset) {{
for u in (0, 1):
for b in (0, 1):
for w in (0, 1):
- (new_header_output,
- new_decoder_output,
- new_decode_block,
- new_exec_output) = buildMode2Inst(p, u, b, w, 0,
- suffix, offset)
- header_output += new_header_output
- decoder_output += new_decoder_output
- exec_output += new_exec_output
- decode_block += '''
- case %#x:
- {%s}
- break;
- ''' % (buildPUBWLCase(p,u,b,w,0), new_decode_block)
-
post = (p == 0)
user = (p == 0 and w == 0)
writeback = (p == 0 or w == 1)
@@ -272,21 +131,31 @@ def format AddrMode2(imm, suffix, offset) {{
if imm:
newDecode = "return new %s(machInst, RD, RN," + \
"%s, machInst.immed11_0);"
- className = loadImmClassName(post, add, writeback,
+ loadClass = loadImmClassName(post, add, writeback,
size, False, user)
- newDecode = newDecode % (className, addStr)
+ storeClass = storeImmClassName(post, add, writeback,
+ size, False, user)
+ loadDecode = newDecode % (loadClass, addStr)
+ storeDecode = newDecode % (storeClass, addStr)
else:
newDecode = "return new %s(machInst, RD, RN, %s," + \
"machInst.shiftSize," + \
"machInst.shift, RM);"
- className = loadRegClassName(post, add, writeback,
+ loadClass = loadRegClassName(post, add, writeback,
size, False, user)
- newDecode = newDecode % (className, addStr)
- decode_block += '''
+ storeClass = storeRegClassName(post, add, writeback,
+ size, False, user)
+ loadDecode = newDecode % (loadClass, addStr)
+ storeDecode = newDecode % (storeClass, addStr)
+ decode = '''
case %#x:
{%s}
break;
- ''' % (buildPUBWLCase(p,u,b,w,1), newDecode)
+ '''
+ decode_block += decode % \
+ (buildPUBWLCase(p,u,b,w,1), loadDecode)
+ decode_block += decode % \
+ (buildPUBWLCase(p,u,b,w,0), storeDecode)
decode_block += '''
default:
return new Unknown(machInst);
diff --git a/src/arch/arm/isa/insts/insts.isa b/src/arch/arm/isa/insts/insts.isa
index 8c1304af0..404a63328 100644
--- a/src/arch/arm/isa/insts/insts.isa
+++ b/src/arch/arm/isa/insts/insts.isa
@@ -45,3 +45,6 @@
//Loads of a single item
##include "ldr.isa"
+
+//Stores of a single item
+##include "str.isa"
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
new file mode 100644
index 000000000..a051b0e72
--- /dev/null
+++ b/src/arch/arm/isa/insts/str.isa
@@ -0,0 +1,139 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder. You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+let {{
+
+ header_output = ""
+ decoder_output = ""
+ exec_output = ""
+
+ def storeImmClassName(post, add, writeback, \
+ size=4, sign=False, user=False):
+ return memClassName("STORE_IMM", post, add, writeback,
+ size, sign, user)
+
+ def storeRegClassName(post, add, writeback, \
+ size=4, sign=False, user=False):
+ return memClassName("STORE_REG", post, add, writeback,
+ size, sign, user)
+
+ def emitStore(name, Name, imm, eaCode, accCode, memFlags, instFlags, base):
+ global header_output, decoder_output, exec_output
+
+ (newHeader,
+ newDecoder,
+ newExec) = newLoadStoreBase(name, Name, imm,
+ eaCode, accCode,
+ memFlags, instFlags,
+ base, execTemplateBase = 'Store')
+
+ header_output += newHeader
+ decoder_output += newDecoder
+ exec_output += newExec
+
+ def buildImmStore(mnem, post, add, writeback, \
+ size=4, sign=False, user=False):
+ name = mnem
+ Name = storeImmClassName(post, add, writeback, \
+ size, sign, user)
+
+ if add:
+ op = " +"
+ else:
+ op = " -"
+
+ offset = op + " imm"
+ eaCode = "EA = Base"
+ if not post:
+ eaCode += offset
+ eaCode += ";"
+
+ accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
+ if writeback:
+ accCode += "Base = Base %s;\n" % offset
+ base = buildMemBase("MemoryNewImm", post, writeback)
+
+ emitStore(name, Name, True, eaCode, accCode, [], [], base)
+
+ def buildRegStore(mnem, post, add, writeback, \
+ size=4, sign=False, user=False):
+ name = mnem
+ Name = storeRegClassName(post, add, writeback,
+ size, sign, user)
+
+ if add:
+ op = " +"
+ else:
+ op = " -"
+
+ offset = op + " shift_rm_imm(Index, shiftAmt," + \
+ " shiftType, CondCodes<29:>)"
+ eaCode = "EA = Base"
+ if not post:
+ eaCode += offset
+ eaCode += ";"
+
+ accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
+ if writeback:
+ accCode += "Base = Base %s;\n" % offset
+ base = buildMemBase("MemoryNewReg", post, writeback)
+
+ emitStore(name, Name, False, eaCode, accCode, [], [], base)
+
+ def buildStores(mnem, size=4, sign=False, user=False):
+ buildImmStore(mnem, True, True, True, size, sign, user)
+ buildRegStore(mnem, True, True, True, size, sign, user)
+ buildImmStore(mnem, True, False, True, size, sign, user)
+ buildRegStore(mnem, True, False, True, size, sign, user)
+ buildImmStore(mnem, False, True, True, size, sign, user)
+ buildRegStore(mnem, False, True, True, size, sign, user)
+ buildImmStore(mnem, False, False, True, size, sign, user)
+ buildRegStore(mnem, False, False, True, size, sign, user)
+ buildImmStore(mnem, False, True, False, size, sign, user)
+ buildRegStore(mnem, False, True, False, size, sign, user)
+ buildImmStore(mnem, False, False, False, size, sign, user)
+ buildRegStore(mnem, False, False, False, size, sign, user)
+
+ buildStores("str")
+ buildStores("strt", user=True)
+ buildStores("strb", size=1)
+ buildStores("strbt", size=1, user=True)
+ buildStores("strh", size=2)
+ buildStores("strht", size=2, user=True)
+}};
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index c8faca783..b424072bc 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -1,5 +1,17 @@
// -*- mode:c++ -*-
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder. You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
@@ -56,6 +68,71 @@ def template LoadExecute {{
}
}};
+def template StoreExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+
+ if (%(predicate_test)s)
+ {
+ if (fault == NoFault) {
+ %(memacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
+ memAccessFlags, NULL);
+ if (traceData) { traceData->setData(Mem); }
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+ }
+
+ return fault;
+ }
+}};
+
+def template StoreInitiateAcc {{
+ Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+
+ if (%(predicate_test)s)
+ {
+ if (fault == NoFault) {
+ %(memacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
+ memAccessFlags, NULL);
+ if (traceData) { traceData->setData(Mem); }
+ }
+
+ // Need to write back any potential address register update
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+ }
+
+ return fault;
+ }
+}};
+
def template LoadInitiateAcc {{
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
@@ -106,6 +183,27 @@ def template LoadCompleteAcc {{
}
}};
+def template StoreCompleteAcc {{
+ Fault %(class_name)s::completeAcc(PacketPtr pkt,
+ %(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+ %(op_rd)s;
+
+ if (%(predicate_test)s)
+ {
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+ }
+
+ return fault;
+ }
+}};
+
def template LoadStoreImmDeclare {{
/**
* Static instruction class for "%(mnemonic)s".
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 00:35:17 +0000