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-rw-r--r--src/arch/alpha/regfile.hh3
-rwxr-xr-xsrc/arch/isa_parser.py37
-rw-r--r--src/arch/mips/faults.cc2
-rw-r--r--src/arch/mips/isa/decoder.isa4
4 files changed, 40 insertions, 6 deletions
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index 8a150dc69..792a518fb 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -177,9 +177,6 @@ namespace AlphaISA
intRegFile.setReg(intReg, val);
}
- void setShadowSet(int css)
- { }
-
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index ef21f7ceb..bbdd95bb0 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1235,6 +1235,9 @@ class Operand(object):
def isControlReg(self):
return 0
+ def isIControlReg(self):
+ return 0
+
def getFlags(self):
# note the empty slice '[:]' gives us a copy of self.flags[0]
# instead of a reference to it
@@ -1610,6 +1613,8 @@ def buildOperandNameMap(userDict, lineno):
global operandsWithExtRE
operandsWithExtRE = re.compile(operandsWithExtREString, re.MULTILINE)
+maxInstSrcRegs = 0
+maxInstDestRegs = 0
class OperandList:
@@ -1673,6 +1678,12 @@ class OperandList:
if self.memOperand:
error(0, "Code block has more than one memory operand.")
self.memOperand = op_desc
+ global maxInstSrcRegs
+ global maxInstDestRegs
+ if maxInstSrcRegs < self.numSrcRegs:
+ maxInstSrcRegs = self.numSrcRegs
+ if maxInstDestRegs < self.numDestRegs:
+ maxInstDestRegs = self.numDestRegs
# now make a final pass to finalize op_desc fields that may depend
# on the register enumeration
for op_desc in self.items:
@@ -1892,6 +1903,22 @@ namespace %(namespace)s {
%(decode_function)s
'''
+max_inst_regs_template = '''
+/*
+ * DO NOT EDIT THIS FILE!!!
+ *
+ * It was automatically generated from the ISA description in %(filename)s
+ */
+
+namespace %(namespace)s {
+
+ const int MaxInstSrcRegs = %(MaxInstSrcRegs)d;
+ const int MaxInstDestRegs = %(MaxInstDestRegs)d;
+
+} // namespace %(namespace)s
+
+'''
+
# Update the output file only if the new contents are different from
# the current contents. Minimizes the files that need to be rebuilt
@@ -1991,6 +2018,16 @@ def parse_isa_desc(isa_desc_file, output_dir):
update_if_needed(output_dir + '/' + cpu.filename,
file_template % vars())
+ # The variable names here are hacky, but this will creat local variables
+ # which will be referenced in vars() which have the value of the globals.
+ global maxInstSrcRegs
+ MaxInstSrcRegs = maxInstSrcRegs
+ global maxInstDestRegs
+ MaxInstDestRegs = maxInstDestRegs
+ # max_inst_regs.hh
+ update_if_needed(output_dir + '/max_inst_regs.hh', \
+ max_inst_regs_template % vars())
+
# global list of CpuModel objects (see cpu_models.py)
cpu_models = []
diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 3e1cb69c9..b2778dcd0 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -196,7 +196,7 @@ void MipsFault::setExceptionState(ThreadContext *tc,uint8_t ExcCode)
// Move ESS to CSS
replaceBits(srs,SRSCtl_CSS_HI,SRSCtl_CSS_LO,ESS);
tc->setMiscRegNoEffect(MipsISA::SRSCtl,srs);
- tc->setShadowSet(ESS);
+ //tc->setShadowSet(ESS);
}
// set EXL bit (don't care if it is already set!)
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index eb1b0390a..9a2641138 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -652,7 +652,7 @@ decode OPCODE_HI default Unknown::unknown() {
Status_EXL = 0;
if(Config_AR >=1 && SRSCtl_HSS > 0 && Status_BEV == 0){
SRSCtl_CSS = SRSCtl_PSS;
- xc->setShadowSet(SRSCtl_PSS);
+ //xc->setShadowSet(SRSCtl_PSS);
}
}
LLFlag = 0;
@@ -2086,7 +2086,7 @@ decode OPCODE_HI default Unknown::unknown() {
format CP0Control {
0x7: cache({{
Addr CacheEA = Rs.uw + OFFSET;
- fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA);
+ //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA);
}});
}
}