diff options
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/power/isa/decoder.isa | 36 | ||||
| -rw-r--r-- | src/arch/power/isa/formats/branch.isa | 6 | ||||
| -rw-r--r-- | src/arch/power/isa/operands.isa | 3 |
3 files changed, 11 insertions, 34 deletions
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index 671f57389..336e35d48 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -381,20 +381,12 @@ decode OPCODE default Unknown::unknown() { // Conditionally branch relative to PC based on CR and CTR. format BranchPCRelCondCtr { - 0: bc({{ - PowerISA::PCState pc = PCS; - pc.npc((uint32_t)(pc.pc() + disp)); - PCS = pc; - }}); + 0: bc({{ NPC = (uint32_t)(PC + disp); }}); } // Conditionally branch to fixed address based on CR and CTR. format BranchNonPCRelCondCtr { - 1: bca({{ - PowerISA::PCState pc = PCS; - pc.npc(targetAddr); - PCS = pc; - }}); + 1: bca({{ NPC = targetAddr; }}); } } @@ -402,20 +394,12 @@ decode OPCODE default Unknown::unknown() { // Unconditionally branch relative to PC. format BranchPCRel { - 0: b({{ - PowerISA::PCState pc = PCS; - pc.npc((uint32_t)(pc.pc() + disp)); - PCS = pc; - }}); + 0: b({{ NPC = (uint32_t)(PC + disp); }}); } // Unconditionally branch to fixed address. format BranchNonPCRel { - 1: ba({{ - PowerISA::PCState pc = PCS; - pc.npc(targetAddr); - PCS = pc; - }}); + 1: ba({{ NPC = targetAddr; }}); } } @@ -423,20 +407,12 @@ decode OPCODE default Unknown::unknown() { // Conditionally branch to address in LR based on CR and CTR. format BranchLrCondCtr { - 16: bclr({{ - PowerISA::PCState pc = PCS; - pc.npc(LR & 0xfffffffc); - PCS = pc; - }}); + 16: bclr({{ NPC = LR & 0xfffffffc; }}); } // Conditionally branch to address in CTR based on CR. format BranchCtrCond { - 528: bcctr({{ - PowerISA::PCState pc = PCS; - pc.npc(CTR & 0xfffffffc); - PCS = pc; - }}); + 528: bcctr({{ NPC = CTR & 0xfffffffc; }}); } // Condition register manipulation instructions. diff --git a/src/arch/power/isa/formats/branch.isa b/src/arch/power/isa/formats/branch.isa index da1579ea8..d51ed5c25 100644 --- a/src/arch/power/isa/formats/branch.isa +++ b/src/arch/power/isa/formats/branch.isa @@ -48,7 +48,7 @@ let {{ # Simple code to update link register (LR). -updateLrCode = 'PowerISA::PCState lrpc = PCS; LR = lrpc.pc() + 4;' +updateLrCode = 'LR = PC + 4;' }}; @@ -105,7 +105,7 @@ def GetCondCode(br_code): cond_code = 'if(condOk(CR)) {\n' cond_code += ' ' + br_code + '\n' cond_code += '} else {\n' - cond_code += ' PCS = PCS;\n' + cond_code += ' NPC = NPC;\n' cond_code += '}\n' return cond_code @@ -119,7 +119,7 @@ def GetCtrCondCode(br_code): cond_code += 'if(ctr_ok && cond_ok) {\n' cond_code += ' ' + br_code + '\n' cond_code += '} else {\n' - cond_code += ' PCS = PCS;\n' + cond_code += ' NPC = NPC;\n' cond_code += '}\n' cond_code += 'CTR = ctr;\n' return cond_code diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa index 908e6e0e7..8e13a13d7 100644 --- a/src/arch/power/isa/operands.isa +++ b/src/arch/power/isa/operands.isa @@ -59,7 +59,8 @@ def operands {{ 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8), # Program counter and next - 'PCS': ('PCState', 'uq', None, (None, None, 'IsControl'), 9), + 'PC': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 9), + 'NPC': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 9), # Control registers 'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9), |