4 files changed, 13 insertions, 5 deletions
diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py
index 7cfb549f3..099327470 100644
--- a/src/arch/alpha/AlphaTLB.py
+++ b/src/arch/alpha/AlphaTLB.py
@@ -28,7 +28,10 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-class AlphaTLB(SimObject):
+
+from BaseTLB import BaseTLB
+
+class AlphaTLB(BaseTLB):
     type = 'AlphaTLB'
     abstract = True
     size = Param.Int("TLB size")
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index 0054acae5..41d46c572 100644
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -32,7 +32,9 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
-class MipsTLB(SimObject):
+from BaseTLB import BaseTLB
+
+class MipsTLB(BaseTLB):
     type = 'MipsTLB'
     abstract = True
     size = Param.Int("TLB size")
diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py
index 20672a24e..6758d612a 100644
--- a/src/arch/sparc/SparcTLB.py
+++ b/src/arch/sparc/SparcTLB.py
@@ -28,7 +28,10 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-class SparcTLB(SimObject):
+
+from BaseTLB import BaseTLB
+
+class SparcTLB(BaseTLB):
     type = 'SparcTLB'
     abstract = True
     size = Param.Int("TLB size")
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index c20566efb..d5ae95372 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -54,10 +54,10 @@
 # Authors: Gabe Black
 
 from MemObject import MemObject
-from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
 from m5 import build_env
+from BaseTLB import BaseTLB
 
 if build_env['FULL_SYSTEM']:
     class X86PagetableWalker(MemObject):
@@ -66,7 +66,7 @@ if build_env['FULL_SYSTEM']:
         port = Port("Port for the hardware table walker")
         system = Param.System(Parent.any, "system object")
 
-class X86TLB(SimObject):
+class X86TLB(BaseTLB):
     type = 'X86TLB'
     abstract = True
     size = Param.Int("TLB size")