diff options
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/alpha/interrupts.hh | 28 | ||||
-rw-r--r-- | src/arch/alpha/miscregfile.cc | 10 | ||||
-rw-r--r-- | src/arch/alpha/tlb.cc | 2 |
3 files changed, 22 insertions, 18 deletions
diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh index 75031ae47..a86fb2d7b 100644 --- a/src/arch/alpha/interrupts.hh +++ b/src/arch/alpha/interrupts.hh @@ -49,6 +49,7 @@ namespace AlphaISA { memset(interrupts, 0, sizeof(interrupts)); intstatus = 0; + newInfoSet = false; } void post(int int_num, int index) @@ -137,18 +138,10 @@ namespace AlphaISA } if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) { - tc->setMiscReg(IPR_ISR, summary); - tc->setMiscReg(IPR_INTID, ipl); - - /* The following needs to be added back in somehow */ - // Checker needs to know these two registers were updated. -/*#if USE_CHECKER - if (this->checker) { - this->checker->threadBase()->setMiscReg(IPR_ISR, summary); - this->checker->threadBase()->setMiscReg(IPR_INTID, ipl); - } -#endif*/ - +// assert(!newInfoSet); + newIpl = ipl; + newSummary = newSummary; + newInfoSet = true; DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", tc->readMiscReg(IPR_IPLR), ipl, summary); @@ -158,7 +151,18 @@ namespace AlphaISA } } + void updateIntrInfo(ThreadContext *tc) + { + assert(newInfoSet); + tc->setMiscReg(IPR_ISR, newSummary); + tc->setMiscReg(IPR_INTID, newIpl); + newInfoSet = false; + } + private: + bool newInfoSet; + int newIpl; + int newSummary; }; } diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc index 4cf57a690..962d4609f 100644 --- a/src/arch/alpha/miscregfile.cc +++ b/src/arch/alpha/miscregfile.cc @@ -132,7 +132,6 @@ namespace AlphaISA MiscRegFile::setRegWithEffect(int misc_reg, const MiscReg &val, ThreadContext *tc) { -#if FULL_SYSTEM switch(misc_reg) { case MISCREG_FPCR: fpcr = val; @@ -150,12 +149,13 @@ namespace AlphaISA intr_flag = val; return; default: - return setIpr(misc_reg, val, tc); - } +#if FULL_SYSTEM + setIpr(misc_reg, val, tc); #else - //panic("No registers with side effects in SE mode!"); - return; + panic("No registers with side effects in SE mode!"); #endif + return; + } } } diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index ae302e686..af69e45c0 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -292,7 +292,7 @@ namespace AlphaISA Fault ITB::translate(RequestPtr &req, ThreadContext *tc) const { - if (PcPAL(req->getVaddr())) { + if (PcPAL(req->getPC())) { // strip off PAL PC marker (lsb is 1) req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); hits++; |