diff options
Diffstat (limited to 'src/arch')
24 files changed, 82 insertions, 490 deletions
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript index 2d59180c4..4f293e22f 100644 --- a/src/arch/alpha/SConscript +++ b/src/arch/alpha/SConscript @@ -38,12 +38,12 @@ if env['TARGET_ISA'] == 'alpha': Source('miscregfile.cc') Source('regfile.cc') Source('remote_gdb.cc') + Source('utility.cc') if env['FULL_SYSTEM']: SimObject('AlphaSystem.py') SimObject('AlphaTLB.py') - Source('arguments.cc') Source('ev5.cc') Source('idle_event.cc') Source('ipr.cc') diff --git a/src/arch/alpha/arguments.hh b/src/arch/alpha/arguments.hh deleted file mode 100644 index 4dba4901f..000000000 --- a/src/arch/alpha/arguments.hh +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -#ifndef __ARCH_ALPHA_ARGUMENTS_HH__ -#define __ARCH_ALPHA_ARGUMENTS_HH__ - -#include <assert.h> - -#include "arch/alpha/vtophys.hh" -#include "base/refcnt.hh" -#include "mem/vport.hh" -#include "sim/host.hh" - -class ThreadContext; - -namespace AlphaISA { - -class Arguments -{ - protected: - ThreadContext *tc; - int number; - uint64_t getArg(bool fp = false); - - protected: - class Data : public RefCounted - { - public: - Data(){} - ~Data(); - - private: - std::list<char *> data; - - public: - char *alloc(size_t size); - }; - - RefCountingPtr<Data> data; - - public: - Arguments(ThreadContext *ctx, int n = 0) - : tc(ctx), number(n), data(NULL) - { assert(number >= 0); data = new Data;} - Arguments(const Arguments &args) - : tc(args.tc), number(args.number), data(args.data) {} - ~Arguments() {} - - ThreadContext *getThreadContext() const { return tc; } - - const Arguments &operator=(const Arguments &args) { - tc = args.tc; - number = args.number; - data = args.data; - return *this; - } - - Arguments &operator++() { - ++number; - assert(number >= 0); - return *this; - } - - Arguments operator++(int) { - Arguments args = *this; - ++number; - assert(number >= 0); - return args; - } - - Arguments &operator--() { - --number; - assert(number >= 0); - return *this; - } - - Arguments operator--(int) { - Arguments args = *this; - --number; - assert(number >= 0); - return args; - } - - const Arguments &operator+=(int index) { - number += index; - assert(number >= 0); - return *this; - } - - const Arguments &operator-=(int index) { - number -= index; - assert(number >= 0); - return *this; - } - - Arguments operator[](int index) { - return Arguments(tc, index); - } - - template <class T> - operator T() { - assert(sizeof(T) <= sizeof(uint64_t)); - T data = static_cast<T>(getArg()); - return data; - } - - template <class T> - operator T *() { - T *buf = (T *)data->alloc(sizeof(T)); - CopyData(tc, buf, getArg(), sizeof(T)); - return buf; - } - - operator char *() { - char *buf = data->alloc(2048); - CopyStringOut(tc, buf, getArg(), 2048); - return buf; - } -}; - -}; // namespace AlphaISA - -#endif // __ARCH_ALPHA_ARGUMENTS_HH__ diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index af1a91a62..2177e8c4f 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -714,7 +714,7 @@ decode OPCODE default Unknown::unknown() { }}, IsNonSpeculative); 0x83: callsys({{ xc->syscall(R0); - }}, IsSerializeAfter, IsNonSpeculative); + }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); // Read uniq reg into ABI return value register (r0) 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess); // Write uniq reg with value from ABI arg register (r16) diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc index f93cdfbad..102598716 100644 --- a/src/arch/alpha/linux/system.cc +++ b/src/arch/alpha/linux/system.cc @@ -40,7 +40,6 @@ * up boot time. */ -#include "arch/arguments.hh" #include "arch/vtophys.hh" #include "arch/alpha/idle_event.hh" #include "arch/alpha/linux/system.hh" @@ -54,6 +53,7 @@ #include "kern/linux/events.hh" #include "mem/physical.hh" #include "mem/port.hh" +#include "sim/arguments.hh" #include "sim/byteswap.hh" using namespace std; diff --git a/src/arch/alpha/arguments.cc b/src/arch/alpha/utility.cc index e89bd70b0..f1864203b 100644 --- a/src/arch/alpha/arguments.cc +++ b/src/arch/alpha/utility.cc @@ -26,45 +26,40 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Nathan Binkert + * Ali Saidi */ -#include "arch/alpha/arguments.hh" +#include "arch/alpha/utility.hh" + +#if FULL_SYSTEM #include "arch/alpha/vtophys.hh" -#include "cpu/thread_context.hh" #include "mem/vport.hh" +#endif -using namespace AlphaISA; - -Arguments::Data::~Data() -{ - while (!data.empty()) { - delete [] data.front(); - data.pop_front(); - } -} - -char * -Arguments::Data::alloc(size_t size) +namespace AlphaISA { - char *buf = new char[size]; - data.push_back(buf); - return buf; -} -uint64_t -Arguments::getArg(bool fp) +uint64_t getArgument(ThreadContext *tc, int number, bool fp) { - if (number < 6) { +#if FULL_SYSTEM + if (number < NumArgumentRegs) { if (fp) - return tc->readFloatRegBits(16 + number); + return tc->readFloatRegBits(ArgumentReg[number]); else - return tc->readIntReg(16 + number); + return tc->readIntReg(ArgumentReg[number]); } else { - Addr sp = tc->readIntReg(30); + Addr sp = tc->readIntReg(StackPointerReg); VirtualPort *vp = tc->getVirtPort(tc); - uint64_t arg = vp->read<uint64_t>(sp + (number-6) * sizeof(uint64_t)); + uint64_t arg = vp->read<uint64_t>(sp + + (number-NumArgumentRegs) * sizeof(uint64_t)); tc->delVirtPort(vp); return arg; } +#else + panic("getArgument() is Full system only\n"); + M5_DUMMY_RETURN +#endif } +} // namespace AlphaISA + diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index c20394a92..5d461a0f9 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -42,6 +42,8 @@ namespace AlphaISA { + uint64_t getArgument(ThreadContext *tc, int number, bool fp); + static inline bool inUserMode(ThreadContext *tc) { diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript index de209348a..658710389 100644 --- a/src/arch/mips/SConscript +++ b/src/arch/mips/SConscript @@ -34,8 +34,9 @@ Import('*') if env['TARGET_ISA'] == 'mips': Source('faults.cc') - Source('isa_traits.cc') + Source('regfile/int_regfile.cc') Source('regfile/misc_regfile.cc') + Source('regfile/regfile.cc') Source('utility.cc') Source('dsp.cc') diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index e55d2e070..40ea223f6 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -134,7 +134,8 @@ decode OPCODE_HI default Unknown::unknown() { 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 0x4: syscall({{ xc->syscall(R2); }}, - IsSerializeAfter, IsNonSpeculative); + IsSerializeAfter, IsNonSpeculative, + IsSyscall); 0x7: sync({{ ; }}, IsMemBarrier); } diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa index 0e0cf44eb..0ce807a24 100644 --- a/src/arch/mips/isa/includes.isa +++ b/src/arch/mips/isa/includes.isa @@ -72,6 +72,7 @@ output exec {{ #include "arch/mips/dsp.hh" #include "arch/mips/pra_constants.hh" #include "arch/mips/dt_constants.hh" +#include "arch/mips/mt.hh" #include "arch/mips/mt_constants.hh" #include <math.h> diff --git a/src/arch/mips/isa_traits.cc b/src/arch/mips/isa_traits.cc deleted file mode 100644 index 0c84ce2b2..000000000 --- a/src/arch/mips/isa_traits.cc +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Korey Sewell - */ - -#include "arch/mips/isa_traits.hh" -#include "arch/mips/regfile/regfile.hh" -#include "sim/serialize.hh" -#include "base/bitfield.hh" - -using namespace MipsISA; -using namespace std; - -void -MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest) -{ - panic("Copy Regs Not Implemented Yet\n"); -} - -void -MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest) -{ - panic("Copy Misc. Regs Not Implemented Yet\n"); -} - -void -MipsISA::MiscRegFile::copyMiscRegs(ThreadContext *tc) -{ - panic("Copy Misc. Regs Not Implemented Yet\n"); -} - -void -IntRegFile::serialize(std::ostream &os) -{ - SERIALIZE_ARRAY(regs, NumIntRegs); -} - -void -IntRegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - UNSERIALIZE_ARRAY(regs, NumIntRegs); -} - -void -RegFile::serialize(std::ostream &os) -{ - intRegFile.serialize(os); - //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs); - //SERIALZE_ARRAY(miscRegFile); - //SERIALIZE_SCALAR(miscRegs.fpcr); - //SERIALIZE_SCALAR(miscRegs.lock_flag); - //SERIALIZE_SCALAR(miscRegs.lock_addr); - SERIALIZE_SCALAR(pc); - SERIALIZE_SCALAR(npc); - SERIALIZE_SCALAR(nnpc); -} - - -void -RegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - intRegFile.unserialize(cp, section); - //UNSERIALIZE_ARRAY(floatRegFile); - //UNSERIALZE_ARRAY(miscRegFile); - //UNSERIALIZE_SCALAR(miscRegs.fpcr); - //UNSERIALIZE_SCALAR(miscRegs.lock_flag); - //UNSERIALIZE_SCALAR(miscRegs.lock_addr); - UNSERIALIZE_SCALAR(pc); - UNSERIALIZE_SCALAR(npc); - UNSERIALIZE_SCALAR(nnpc); - -} - - diff --git a/src/arch/mips/mt_constants.hh b/src/arch/mips/mt_constants.hh index 0f6978433..57306d237 100755 --- a/src/arch/mips/mt_constants.hh +++ b/src/arch/mips/mt_constants.hh @@ -31,7 +31,6 @@ #ifndef __ARCH_MIPS_MT_CONSTANTS_HH__ #define __ARCH_MIPS_MT_CONSTANTS_HH__ -#include "arch/mips/types.hh" //#include "config/full_system.hh" namespace MipsISA diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc index 71be3adf9..02e9c92bb 100755 --- a/src/arch/mips/regfile/misc_regfile.cc +++ b/src/arch/mips/regfile/misc_regfile.cc @@ -30,13 +30,13 @@ #include "base/bitfield.hh" -#include "arch/mips/regfile/misc_regfile.hh" -#include "arch/mips/mt_constants.hh" #include "arch/mips/faults.hh" +#include "arch/mips/mt.hh" +#include "arch/mips/mt_constants.hh" +#include "arch/mips/regfile/misc_regfile.hh" -#include "cpu/thread_context.hh" #include "cpu/base.hh" -#include "cpu/exetrace.hh" +#include "cpu/thread_context.hh" //#include "cpu/mixie/cpu.hh" using namespace std; diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh index 54b086a8b..0846378bb 100644 --- a/src/arch/mips/regfile/misc_regfile.hh +++ b/src/arch/mips/regfile/misc_regfile.hh @@ -33,14 +33,12 @@ #include "arch/mips/isa_traits.hh" #include "arch/mips/types.hh" -#include "arch/mips/mt.hh" -#include "arch/mips/mt_constants.hh" -#include "base/bitfield.hh" -#include "cpu/base.hh" +#include "sim/eventq.hh" #include "sim/faults.hh" #include <queue> class ThreadContext; +class BaseCPU; namespace MipsISA { @@ -76,7 +74,10 @@ namespace MipsISA void expandForMultithreading(unsigned num_threads, unsigned num_vpes); - void copyMiscRegs(ThreadContext *tc); + void copyMiscRegs(ThreadContext *tc) + { + panic("Copy Misc. Regs Not Implemented Yet\n"); + } inline unsigned getVPENum(unsigned tid); diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh index f13653132..b83bb576b 100644 --- a/src/arch/mips/regfile/regfile.hh +++ b/src/arch/mips/regfile/regfile.hh @@ -32,8 +32,6 @@ #define __ARCH_MIPS_REGFILE_REGFILE_HH__ #include "arch/mips/types.hh" -#include "arch/mips/isa_traits.hh" -#include "arch/mips/mt.hh" #include "arch/mips/regfile/int_regfile.hh" #include "arch/mips/regfile/float_regfile.hh" #include "arch/mips/regfile/misc_regfile.hh" @@ -189,9 +187,11 @@ namespace MipsISA return reg; } - void copyRegs(ThreadContext *src, ThreadContext *dest); + void + copyRegs(ThreadContext *src, ThreadContext *dest); - void copyMiscRegs(ThreadContext *src, ThreadContext *dest); + void + copyMiscRegs(ThreadContext *src, ThreadContext *dest); } // namespace MipsISA diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh index e3fd9daa8..300761c93 100644 --- a/src/arch/mips/utility.hh +++ b/src/arch/mips/utility.hh @@ -48,6 +48,10 @@ class ThreadContext; namespace MipsISA { + uint64_t getArgument(ThreadContext *tc, bool fp) { + panic("getArgument() not implemented for MIPS\n"); + } + //Floating Point Utility Functions uint64_t fpConvert(ConvertType cvt_type, double fp_val); double roundFP(double val, int digits); @@ -70,8 +74,6 @@ namespace MipsISA { void startupCPU(ThreadContext *tc, int cpuId); - void copyRegs(ThreadContext *src, ThreadContext *dest); - // Instruction address compression hooks static inline Addr realPCToFetchPC(const Addr &addr) { return addr; diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index c9dbb8cf2..0552c282b 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -39,12 +39,12 @@ if env['TARGET_ISA'] == 'sparc': Source('miscregfile.cc') Source('regfile.cc') Source('remote_gdb.cc') + Source('utility.cc') if env['FULL_SYSTEM']: SimObject('SparcSystem.py') SimObject('SparcTLB.py') - Source('arguments.cc') Source('pagetable.cc') Source('stacktrace.cc') Source('system.cc') diff --git a/src/arch/sparc/arguments.hh b/src/arch/sparc/arguments.hh deleted file mode 100644 index 5596f7408..000000000 --- a/src/arch/sparc/arguments.hh +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -#ifndef __ARCH_SPARC_ARGUMENTS_HH__ -#define __ARCH_SPARC_ARGUMENTS_HH__ - -#include <assert.h> - -#include "base/refcnt.hh" -#include "sim/host.hh" -#include "mem/vport.hh" - -class ThreadContext; - -namespace SparcISA { - -class Arguments -{ - protected: - ThreadContext *tc; - int number; - uint64_t getArg(bool fp = false); - - protected: - class Data : public RefCounted - { - public: - Data(){} - ~Data(); - - private: - std::list<char *> data; - - public: - char *alloc(size_t size); - }; - - RefCountingPtr<Data> data; - - public: - Arguments(ThreadContext *ctx, int n = 0) - : tc(ctx), number(n), data(NULL) - { assert(number >= 0); data = new Data;} - Arguments(const Arguments &args) - : tc(args.tc), number(args.number), data(args.data) {} - ~Arguments() {} - - ThreadContext *getThreadContext() const { return tc; } - - const Arguments &operator=(const Arguments &args) { - tc = args.tc; - number = args.number; - data = args.data; - return *this; - } - - Arguments &operator++() { - ++number; - assert(number >= 0); - return *this; - } - - Arguments operator++(int) { - Arguments args = *this; - ++number; - assert(number >= 0); - return args; - } - - Arguments &operator--() { - --number; - assert(number >= 0); - return *this; - } - - Arguments operator--(int) { - Arguments args = *this; - --number; - assert(number >= 0); - return args; - } - - const Arguments &operator+=(int index) { - number += index; - assert(number >= 0); - return *this; - } - - const Arguments &operator-=(int index) { - number -= index; - assert(number >= 0); - return *this; - } - - Arguments operator[](int index) { - return Arguments(tc, index); - } - - template <class T> - operator T() { - assert(sizeof(T) <= sizeof(uint64_t)); - T data = static_cast<T>(getArg()); - return data; - } - - template <class T> - operator T *() { - T *buf = (T *)data->alloc(sizeof(T)); - CopyData(tc, buf, getArg(), sizeof(T)); - return buf; - } - - operator char *() { - char *buf = data->alloc(2048); - CopyStringOut(tc, buf, getArg(), 2048); - return buf; - } -}; - -}; // namespace SparcISA - -#endif // __ARCH_SPARC_ARGUMENTS_HH__ diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 68b2183ad..14c652606 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1230,7 +1230,7 @@ decode OP default Unknown::unknown() DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); fault = new TrapInstruction(lTrapNum); } - }}, IsSerializeAfter, IsNonSpeculative); + }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 0x2: Trap::tccx({{ if(passesCondition(Ccr<7:4>, COND2)) { @@ -1238,7 +1238,7 @@ decode OP default Unknown::unknown() DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); fault = new TrapInstruction(lTrapNum); } - }}, IsSerializeAfter, IsNonSpeculative); + }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); } 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, MemWriteOp); diff --git a/src/arch/sparc/arguments.cc b/src/arch/sparc/utility.cc index 44adf4a15..6d4358603 100644 --- a/src/arch/sparc/arguments.cc +++ b/src/arch/sparc/utility.cc @@ -25,49 +25,40 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Nathan Binkert + * Authors: Gabe Black + * Ali Saidi */ -#include "arch/sparc/arguments.hh" +#include "arch/sparc/utility.hh" +#if FULL_SYSTEM #include "arch/sparc/vtophys.hh" -#include "cpu/thread_context.hh" #include "mem/vport.hh" +#endif -using namespace SparcISA; +namespace SparcISA { -Arguments::Data::~Data() -{ - while (!data.empty()) { - delete [] data.front(); - data.pop_front(); - } -} -char * -Arguments::Data::alloc(size_t size) -{ - char *buf = new char[size]; - data.push_back(buf); - return buf; -} - -uint64_t -Arguments::getArg(bool fp) -{ - //The caller uses %o0-%05 for the first 6 arguments even if their floating - //point. Double precision floating point values take two registers/args. - //Quads, structs, and unions are passed as pointers. All arguments beyond - //the sixth are passed on the stack past the 16 word window save area, - //space for the struct/union return pointer, and space reserved for the - //first 6 arguments which the caller may use but doesn't have to. - if (number < 6) { - return tc->readIntReg(8 + number); +//The caller uses %o0-%05 for the first 6 arguments even if their floating +//point. Double precision floating point values take two registers/args. +//Quads, structs, and unions are passed as pointers. All arguments beyond +//the sixth are passed on the stack past the 16 word window save area, +//space for the struct/union return pointer, and space reserved for the +//first 6 arguments which the caller may use but doesn't have to. +uint64_t getArgument(ThreadContext *tc, int number, bool fp) { +#if FULL_SYSTEM + if (number < NumArgumentRegs) { + return tc->readIntReg(ArgumentReg[number]); } else { - Addr sp = tc->readIntReg(14); + Addr sp = tc->readIntReg(StackPointerReg); VirtualPort *vp = tc->getVirtPort(tc); - uint64_t arg = vp->read<uint64_t>(sp + 92 + (number-6) * sizeof(uint64_t)); + uint64_t arg = vp->read<uint64_t>(sp + 92 + + (number-NumArgumentRegs) * sizeof(uint64_t)); tc->delVirtPort(vp); return arg; } +#else + panic("getArgument() only implemented for FULL_SYSTEM\n"); + M5_DUMMY_RETURN +#endif } - +} //namespace SPARC_ISA diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index 1458231f2..9a84a82b3 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -41,6 +41,9 @@ namespace SparcISA { + + uint64_t getArgument(ThreadContext *tc, int number, bool fp); + static inline bool inUserMode(ThreadContext *tc) { diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index a8c4e7062..e8307c6e6 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -70,7 +70,7 @@ #if FULL_SYSTEM 0x05: syscall(); #else - 0x05: SyscallInst::syscall('xc->syscall(rax)'); + 0x05: SyscallInst::syscall('xc->syscall(rax)', IsSyscall); #endif 0x06: clts(); //sandpile.org says (AMD) after sysret, so I might want to check diff --git a/src/arch/x86/isa/decoder/x87.isa b/src/arch/x86/isa/decoder/x87.isa index f16647fe5..bab687acd 100644 --- a/src/arch/x86/isa/decoder/x87.isa +++ b/src/arch/x86/isa/decoder/x87.isa @@ -103,7 +103,7 @@ 0x5: fldln2(); 0x6: fldz(); } - default: fldcw(); + default: fldcw_Mw(); } 0x6: decode MODRM_MOD { 0x3: decode MODRM_RM { @@ -129,7 +129,7 @@ 0x6: fsin(); 0x7: fcos(); } - default: fnstcw(); + default: fnstcw_Mw(); } } //0x2: esc2(); diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 18cbc6082..b8cddb09b 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -170,7 +170,7 @@ def template MicroLoadCompleteAcc {{ %(op_rd)s; Mem = pkt->get<typeof(Mem)>(); - int offset = pkt->flags; + int offset = pkt->req->getFlags(); Mem = bits(Mem, (offset + dataSize) * 8 - 1, offset * 8); %(code)s; diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc index 036805612..17904cb33 100644 --- a/src/arch/x86/process.cc +++ b/src/arch/x86/process.cc @@ -412,11 +412,6 @@ X86LiveProcess::argsInit(int intSize, int pageSize) initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); - //Set up the thread context to start running the process - //Because of the peculiarities of how syscall works, I believe - //a process starts with r11 containing the value of eflags or maybe r11 - //from before the call to execve. Empirically this value is 0x200. - threadContexts[0]->setIntReg(INTREG_R11, 0x200); //Set the stack pointer register threadContexts[0]->setIntReg(StackPointerReg, stack_min); |