diff options
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 3 | ||||
| -rw-r--r-- | src/arch/arm/isa/templates/misc.isa | 3 | ||||
| -rw-r--r-- | src/arch/arm/tlb.cc | 4 |
3 files changed, 6 insertions, 4 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index f2a80a111..5742f84ab 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -671,7 +671,8 @@ let {{ exec_output += PredOpExecute.subst(setendIop) clrexCode = ''' - unsigned memAccessFlags = Request::CLREX|3|Request::LLSC; + unsigned memAccessFlags = Request::CLEAR_LL | + ArmISA::TLB::AlignWord | Request::LLSC; fault = xc->read(0, (uint32_t&)Mem, memAccessFlags); ''' clrexIop = InstObjParams("clrex", "Clrex","PredOp", diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa index 46af3f5b1..f8dac05f8 100644 --- a/src/arch/arm/isa/templates/misc.isa +++ b/src/arch/arm/isa/templates/misc.isa @@ -367,7 +367,8 @@ def template ClrexInitiateAcc {{ if (%(predicate_test)s) { if (fault == NoFault) { - unsigned memAccessFlags = Request::CLREX|3|Request::LLSC; + unsigned memAccessFlags = Request::CLEAR_LL | + ArmISA::TLB::AlignWord | Request::LLSC; fault = xc->read(0, (uint32_t&)Mem, memAccessFlags); } } else { diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 4e98aaf7b..c0ebb52b2 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -376,10 +376,10 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, // If this is a clrex instruction, provide a PA of 0 with no fault // This will force the monitor to set the tracked address to 0 // a bit of a hack but this effectively clrears this processors monitor - if (flags & Request::CLREX){ + if (flags & Request::CLEAR_LL){ req->setPaddr(0); req->setFlags(Request::UNCACHEABLE); - req->setFlags(Request::CLREX); + req->setFlags(Request::CLEAR_LL); return NoFault; } if ((req->isInstFetch() && (!sctlr.i)) || |