4 files changed, 42 insertions, 61 deletions

diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index 8599fa75f..9572d2091 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -47,9 +47,6 @@ class ArmTableWalker(MemObject):
     cxx_class = 'ArmISA::TableWalker'
     port = MasterPort("Port for TableWalker to do walk the translation with")
     sys = Param.System(Parent.any, "system object parameter")
-    min_backoff = Param.Tick(0, "Minimum backoff delay after failed send")
-    max_backoff = Param.Tick(100000, "Minimum backoff delay after failed send")
-
 
 class ArmTLB(SimObject):
     type = 'ArmTLB'
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 7dbe92d9b..ea71e6f1c 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -51,8 +51,7 @@
 using namespace ArmISA;
 
 TableWalker::TableWalker(const Params *p)
-    : MemObject(p), port(this, params()->sys, params()->min_backoff,
-                         params()->max_backoff), drainEvent(NULL),
+    : MemObject(p), port(this, params()->sys), drainEvent(NULL),
       tlb(NULL), currState(NULL), pending(false),
       masterId(p->sys->getMasterId(name())),
       doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this)
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 1b95182c8..b6fee66ff 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -287,9 +287,8 @@ class TableWalker : public MemObject
          * A snooping DMA port merely calls the construtor of the DMA
          * port.
          */
-        SnoopingDmaPort(MemObject *dev, System *s, Tick min_backoff,
-                        Tick max_backoff) :
-            DmaPort(dev, s, min_backoff, max_backoff)
+        SnoopingDmaPort(MemObject *dev, System *s) :
+            DmaPort(dev, s)
         { }
     };
 
diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc
index b6e6c33f4..46d608ace 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -570,63 +570,49 @@ bool
 Walker::WalkerState::recvPacket(PacketPtr pkt)
 {
     assert(pkt->isResponse());
-    if (!pkt->wasNacked()) {
-        assert(inflight);
-        assert(state == Waiting);
-        assert(!read);
-        inflight--;
-        if (pkt->isRead()) {
-            state = nextState;
-            nextState = Ready;
-            PacketPtr write = NULL;
-            read = pkt;
-            timingFault = stepWalk(write);
-            state = Waiting;
-            assert(timingFault == NoFault || read == NULL);
-            if (write) {
-                writes.push_back(write);
-            }
-            sendPackets();
-        } else {
-            sendPackets();
-        }
-        if (inflight == 0 && read == NULL && writes.size() == 0) {
-            state = Ready;
-            nextState = Waiting;
-            if (timingFault == NoFault) {
-                /*
-                 * Finish the translation. Now that we now the right entry is
-                 * in the TLB, this should work with no memory accesses.
-                 * There could be new faults unrelated to the table walk like
-                 * permissions violations, so we'll need the return value as
-                 * well.
-                 */
-                bool delayedResponse;
-                Fault fault = walker->tlb->translate(req, tc, NULL, mode,
-                        delayedResponse, true);
-                assert(!delayedResponse);
-                // Let the CPU continue.
-                translation->finish(fault, req, tc, mode);
-            } else {
-                // There was a fault during the walk. Let the CPU know.
-                translation->finish(timingFault, req, tc, mode);
-            }
-            return true;
+    assert(inflight);
+    assert(state == Waiting);
+    assert(!read);
+    inflight--;
+    if (pkt->isRead()) {
+        state = nextState;
+        nextState = Ready;
+        PacketPtr write = NULL;
+        read = pkt;
+        timingFault = stepWalk(write);
+        state = Waiting;
+        assert(timingFault == NoFault || read == NULL);
+        if (write) {
+            writes.push_back(write);
         }
+        sendPackets();
     } else {
-        DPRINTF(PageTableWalker, "Request was nacked. Entering retry state\n");
-        pkt->reinitNacked();
-        if (!walker->sendTiming(this, pkt)) {
-            inflight--;
-            retrying = true;
-            if (pkt->isWrite()) {
-                writes.push_back(pkt);
-            } else {
-                assert(!read);
-                read = pkt;
-            }
+        sendPackets();
+    }
+    if (inflight == 0 && read == NULL && writes.size() == 0) {
+        state = Ready;
+        nextState = Waiting;
+        if (timingFault == NoFault) {
+            /*
+             * Finish the translation. Now that we now the right entry is
+             * in the TLB, this should work with no memory accesses.
+             * There could be new faults unrelated to the table walk like
+             * permissions violations, so we'll need the return value as
+             * well.
+             */
+            bool delayedResponse;
+            Fault fault = walker->tlb->translate(req, tc, NULL, mode,
+                                                 delayedResponse, true);
+            assert(!delayedResponse);
+            // Let the CPU continue.
+            translation->finish(fault, req, tc, mode);
+        } else {
+            // There was a fault during the walk. Let the CPU know.
+            translation->finish(timingFault, req, tc, mode);
         }
+        return true;
     }
+
     return false;
 }