3 files changed, 43 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa
index 241f9637f..aa38fd426 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -1467,6 +1467,8 @@ namespace Aarch64
                 return decodeNeon3Diff(machInst);
             } else if (bits(machInst, 20, 17) == 0x0) {
                 return decodeNeon2RegMisc(machInst);
+            } else if (bits(machInst, 20, 17) == 0x4) {
+                return decodeCryptoAES(machInst);
             } else if (bits(machInst, 20, 17) == 0x8) {
                 return decodeNeonAcrossLanes(machInst);
             } else {
diff --git a/src/arch/arm/isa/formats/crypto64.isa b/src/arch/arm/isa/formats/crypto64.isa
index 8975c2d93..d155b0421 100644
--- a/src/arch/arm/isa/formats/crypto64.isa
+++ b/src/arch/arm/isa/formats/crypto64.isa
@@ -40,6 +40,9 @@
 let {{
     header_output = '''
     StaticInstPtr
+    decodeCryptoAES(ExtMachInst machInst);
+
+    StaticInstPtr
     decodeCryptoThreeRegSHA(ExtMachInst machInst);
 
     StaticInstPtr
@@ -49,6 +52,29 @@ let {{
     decoder_output = '''
 
     StaticInstPtr
+    decodeCryptoAES(ExtMachInst machInst)
+    {
+        const auto opcode = bits(machInst, 16, 12);
+        const auto size = bits(machInst, 23, 22);
+
+        IntRegIndex rd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
+        IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+
+        if (size) {
+            // UNALLOCATED
+            return new Unknown64(machInst);
+        } else {
+            switch (opcode) {
+              case 0x4: return new AESE64(machInst, rd, rd, rn);
+              case 0x5: return new AESD64(machInst, rd, rd, rn);
+              case 0x6: return new AESMC64(machInst, rd, rn);
+              case 0x7: return new AESIMC64(machInst, rd, rn);
+              default: return new Unknown64(machInst);
+            }
+        }
+    }
+
+    StaticInstPtr
     decodeCryptoTwoRegSHA(ExtMachInst machInst)
     {
         const auto opcode = bits(machInst, 16, 12);
diff --git a/src/arch/arm/isa/insts/crypto64.isa b/src/arch/arm/isa/insts/crypto64.isa
index 1af9263fd..64beaf33d 100644
--- a/src/arch/arm/isa/insts/crypto64.isa
+++ b/src/arch/arm/isa/insts/crypto64.isa
@@ -120,6 +120,11 @@ let {{
         decoder_output += RegRegOpConstructor.subst(cryptoiop)
         exec_output += CryptoPredOpExecute.subst(cryptoiop)
 
+    aeseCode = "crypto.aesEncrypt(output, input, input2);"
+    aesdCode = "crypto.aesDecrypt(output, input, input2);"
+    aesmcCode = "crypto.aesMixColumns(output, input);"
+    aesimcCode = "crypto.aesInvMixColumns(output, input);"
+
     sha1_cCode = "crypto.sha1C(output, input, input2);"
     sha1_pCode = "crypto.sha1P(output, input, input2);"
     sha1_mCode = "crypto.sha1M(output, input, input2);"
@@ -132,6 +137,16 @@ let {{
     sha256_su0Code = "crypto.sha256Su0(output, input);"
     sha256_su1Code = "crypto.sha256Su1(output, input, input2);"
 
+    aes_enabled = cryptoEnabledCheckCode % { "mask" : 0xF0 }
+    cryptoRegRegRegInst("aese", "AESE64", "SimdAesOp",
+                        aes_enabled, aeseCode)
+    cryptoRegRegRegInst("aesd", "AESD64", "SimdAesOp",
+                        aes_enabled, aesdCode)
+    cryptoRegRegInst("aesmc", "AESMC64", "SimdAesMixOp",
+                     aes_enabled, aesmcCode)
+    cryptoRegRegInst("aesimc", "AESIMC64", "SimdAesMixOp",
+                     aes_enabled, aesimcCode)
+
     sha1_enabled = cryptoEnabledCheckCode % { "mask" : 0xF00 }
     cryptoRegRegRegInst("sha1c", "SHA1C64", "SimdSha1HashOp",
                         sha1_enabled, sha1_cCode)