2 files changed, 42 insertions, 21 deletions

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9a4fb2805..6063607f0 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -84,12 +84,12 @@ ISA::ISA(Params *p)
         haveLPAE = system->haveLPAE();
         haveVirtualization = system->haveVirtualization();
         haveLargeAsid64 = system->haveLargeAsid64();
-        physAddrRange64 = system->physAddrRange64();
+        physAddrRange = system->physAddrRange();
     } else {
         highestELIs64 = true; // ArmSystem::highestELIs64 does the same
         haveSecurity = haveLPAE = haveVirtualization = false;
         haveLargeAsid64 = false;
-        physAddrRange64 = 32;  // dummy value
+        physAddrRange = 32;  // dummy value
     }
 
     initializeMiscRegMetadata();
@@ -114,22 +114,13 @@ ISA::clear()
     SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
     memset(miscRegs, 0, sizeof(miscRegs));
 
-    // Initialize configurable default values
-    miscRegs[MISCREG_MIDR] = p->midr;
-    miscRegs[MISCREG_MIDR_EL1] = p->midr;
-    miscRegs[MISCREG_VPIDR] = p->midr;
+    initID32(p);
 
-    miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
-    miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
-    miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
-    miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
-    miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
-    miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
-
-    miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
-    miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
-    miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
-    miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
+    // We always initialize AArch64 ID registers even
+    // if we are in AArch32. This is done since if we
+    // are in SE mode we don't know if our ArmProcess is
+    // AArch32 or AArch64
+    initID64(p);
 
     if (FullSystem && system->highestELIs64()) {
         // Initialize AArch64 state
@@ -290,7 +281,32 @@ ISA::clear64(const ArmISAParams *p)
         // Always non-secure
         miscRegs[MISCREG_SCR_EL3] = 1;
     }
+}
+
+void
+ISA::initID32(const ArmISAParams *p)
+{
+    // Initialize configurable default values
+    miscRegs[MISCREG_MIDR] = p->midr;
+    miscRegs[MISCREG_MIDR_EL1] = p->midr;
+    miscRegs[MISCREG_VPIDR] = p->midr;
 
+    miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
+    miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
+    miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
+    miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
+    miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
+    miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
+
+    miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
+    miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
+    miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
+    miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
+}
+
+void
+ISA::initID64(const ArmISAParams *p)
+{
     // Initialize configurable id registers
     miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
     miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
@@ -326,7 +342,7 @@ ISA::clear64(const ArmISAParams *p)
     // Physical address size
     miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
         miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
-        encodePhysAddrRange64(physAddrRange64));
+        encodePhysAddrRange64(physAddrRange));
 }
 
 void
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 7b39682f9..ae35d704c 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -88,7 +88,7 @@ namespace ArmISA
         bool haveLPAE;
         bool haveVirtualization;
         bool haveLargeAsid64;
-        uint8_t physAddrRange64;
+        uint8_t physAddrRange;
 
         /**
          * If true, accesses to IMPLEMENTATION DEFINED registers are treated
@@ -409,8 +409,13 @@ namespace ArmISA
 
       public:
         void clear();
+
+      protected:
         void clear64(const ArmISAParams *p);
+        void initID32(const ArmISAParams *p);
+        void initID64(const ArmISAParams *p);
 
+      public:
         MiscReg readMiscRegNoEffect(int misc_reg) const;
         MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
         void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
@@ -642,7 +647,7 @@ namespace ArmISA
             SERIALIZE_SCALAR(haveLPAE);
             SERIALIZE_SCALAR(haveVirtualization);
             SERIALIZE_SCALAR(haveLargeAsid64);
-            SERIALIZE_SCALAR(physAddrRange64);
+            SERIALIZE_SCALAR(physAddrRange);
         }
         void unserialize(CheckpointIn &cp)
         {
@@ -656,7 +661,7 @@ namespace ArmISA
             UNSERIALIZE_SCALAR(haveLPAE);
             UNSERIALIZE_SCALAR(haveVirtualization);
             UNSERIALIZE_SCALAR(haveLargeAsid64);
-            UNSERIALIZE_SCALAR(physAddrRange64);
+            UNSERIALIZE_SCALAR(physAddrRange);
         }
 
         void startup(ThreadContext *tc);