summaryrefslogtreecommitdiff
path: root/src/arch
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/ArmNativeTrace.py2
-rw-r--r--src/arch/sparc/SparcNativeTrace.py2
-rw-r--r--src/arch/x86/X86NativeTrace.py2
3 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/ArmNativeTrace.py b/src/arch/arm/ArmNativeTrace.py
index 91da1ed76..3101c33de 100644
--- a/src/arch/arm/ArmNativeTrace.py
+++ b/src/arch/arm/ArmNativeTrace.py
@@ -28,7 +28,7 @@
from m5.SimObject import SimObject
from m5.params import *
-from NativeTrace import NativeTrace
+from CPUTracers import NativeTrace
class ArmNativeTrace(NativeTrace):
type = 'ArmNativeTrace'
diff --git a/src/arch/sparc/SparcNativeTrace.py b/src/arch/sparc/SparcNativeTrace.py
index cdc34b541..46b606652 100644
--- a/src/arch/sparc/SparcNativeTrace.py
+++ b/src/arch/sparc/SparcNativeTrace.py
@@ -28,7 +28,7 @@
from m5.SimObject import SimObject
from m5.params import *
-from NativeTrace import NativeTrace
+from CPUTracers import NativeTrace
class SparcNativeTrace(NativeTrace):
type = 'SparcNativeTrace'
diff --git a/src/arch/x86/X86NativeTrace.py b/src/arch/x86/X86NativeTrace.py
index 281a2df50..e6eae8918 100644
--- a/src/arch/x86/X86NativeTrace.py
+++ b/src/arch/x86/X86NativeTrace.py
@@ -28,7 +28,7 @@
from m5.SimObject import SimObject
from m5.params import *
-from NativeTrace import NativeTrace
+from CPUTracers import NativeTrace
class X86NativeTrace(NativeTrace):
type = 'X86NativeTrace'