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-rw-r--r--src/arch/alpha/mmapped_ipr.hh4
-rw-r--r--src/arch/alpha/utility.hh3
-rw-r--r--src/arch/arm/mmapped_ipr.hh4
-rw-r--r--src/arch/arm/table_walker.cc17
-rw-r--r--src/arch/arm/utility.hh2
-rw-r--r--src/arch/mips/isa.cc10
-rw-r--r--src/arch/mips/isa.hh4
-rw-r--r--src/arch/mips/mmapped_ipr.hh4
-rwxr-xr-xsrc/arch/mips/mt.hh2
-rw-r--r--src/arch/mips/utility.cc2
-rw-r--r--src/arch/power/mmapped_ipr.hh4
-rw-r--r--src/arch/power/utility.hh2
-rw-r--r--src/arch/sparc/mmapped_ipr.hh4
-rw-r--r--src/arch/sparc/tlb.cc8
-rw-r--r--src/arch/sparc/tlb.hh4
-rw-r--r--src/arch/sparc/ua2005.cc26
-rw-r--r--src/arch/sparc/utility.hh2
-rw-r--r--src/arch/x86/mmapped_ipr.hh8
-rw-r--r--src/arch/x86/utility.cc6
19 files changed, 59 insertions, 57 deletions
diff --git a/src/arch/alpha/mmapped_ipr.hh b/src/arch/alpha/mmapped_ipr.hh
index 6c3403b33..24f7ce335 100644
--- a/src/arch/alpha/mmapped_ipr.hh
+++ b/src/arch/alpha/mmapped_ipr.hh
@@ -44,14 +44,14 @@ class ThreadContext;
namespace AlphaISA {
-inline Tick
+inline Cycles
handleIprRead(ThreadContext *xc, Packet *pkt)
{
panic("No handleIprRead implementation in Alpha\n");
}
-inline Tick
+inline Cycles
handleIprWrite(ThreadContext *xc, Packet *pkt)
{
panic("No handleIprWrite implementation in Alpha\n");
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index a9b5c4cba..1cd19cc95 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -67,7 +67,8 @@ void zeroRegisters(TC *tc);
// Alpha IPR register accessors
inline bool PcPAL(Addr addr) { return addr & 0x3; }
-inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); }
+inline void startupCPU(ThreadContext *tc, int cpuId)
+{ tc->activate(Cycles(0)); }
////////////////////////////////////////////////////////////////////////
//
diff --git a/src/arch/arm/mmapped_ipr.hh b/src/arch/arm/mmapped_ipr.hh
index 0f90ac35d..474aacbcf 100644
--- a/src/arch/arm/mmapped_ipr.hh
+++ b/src/arch/arm/mmapped_ipr.hh
@@ -46,13 +46,13 @@ class ThreadContext;
namespace ArmISA
{
-inline Tick
+inline Cycles
handleIprRead(ThreadContext *xc, Packet *pkt)
{
panic("No implementation for handleIprRead in ARM\n");
}
-inline Tick
+inline Cycles
handleIprWrite(ThreadContext *xc, Packet *pkt)
{
panic("No implementation for handleIprWrite in ARM\n");
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index ffa193fbe..77cc662b3 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -240,15 +240,16 @@ TableWalker::processWalk()
if (currState->timing) {
port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
&doL1DescEvent, (uint8_t*)&currState->l1Desc.data,
- currState->tc->getCpuPtr()->ticks(1), flag);
- DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n",
+ currState->tc->getCpuPtr()->clockPeriod(), flag);
+ DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before "
+ "adding: %d\n",
stateQueueL1.size());
stateQueueL1.push_back(currState);
currState = NULL;
} else if (!currState->functional) {
port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
NULL, (uint8_t*)&currState->l1Desc.data,
- currState->tc->getCpuPtr()->ticks(1), flag);
+ currState->tc->getCpuPtr()->clockPeriod(), flag);
doL1Descriptor();
f = currState->fault;
} else {
@@ -588,12 +589,12 @@ TableWalker::doL1Descriptor()
if (currState->timing) {
currState->delayed = true;
port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
- &doL2DescEvent, (uint8_t*)&currState->l2Desc.data,
- currState->tc->getCpuPtr()->ticks(1));
+ &doL2DescEvent, (uint8_t*)&currState->l2Desc.data,
+ currState->tc->getCpuPtr()->clockPeriod());
} else if (!currState->functional) {
port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
- NULL, (uint8_t*)&currState->l2Desc.data,
- currState->tc->getCpuPtr()->ticks(1));
+ NULL, (uint8_t*)&currState->l2Desc.data,
+ currState->tc->getCpuPtr()->clockPeriod());
doL2Descriptor();
} else {
RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0,
@@ -758,7 +759,7 @@ void
TableWalker::nextWalk(ThreadContext *tc)
{
if (pendingQueue.size())
- schedule(doProcessEvent, tc->getCpuPtr()->clockEdge(1));
+ schedule(doProcessEvent, tc->getCpuPtr()->clockEdge(Cycles(1)));
}
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index b3b400e3c..e4fc658e0 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -102,7 +102,7 @@ void zeroRegisters(TC *tc);
inline void startupCPU(ThreadContext *tc, int cpuId)
{
- tc->activate(0);
+ tc->activate(Cycles(0));
}
void copyRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 6a525ed3a..f6de102cd 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -482,7 +482,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val,
miscRegFile[misc_reg][reg_sel] = cp0_val;
- scheduleCP0Update(tc->getCpuPtr(), 1);
+ scheduleCP0Update(tc->getCpuPtr(), Cycles(1));
}
/**
@@ -511,14 +511,14 @@ ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
}
void
-ISA::scheduleCP0Update(BaseCPU *cpu, int delay)
+ISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay)
{
if (!cp0Updated) {
cp0Updated = true;
//schedule UPDATE
CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
- cpu->schedule(cp0_event, curTick() + cpu->ticks(delay));
+ cpu->schedule(cp0_event, cpu->clockEdge(delay));
}
}
@@ -573,9 +573,9 @@ ISA::CP0Event::description() const
}
void
-ISA::CP0Event::scheduleEvent(int delay)
+ISA::CP0Event::scheduleEvent(Cycles delay)
{
- cpu->reschedule(this, curTick() + cpu->ticks(delay), true);
+ cpu->reschedule(this, cpu->clockEdge(delay), true);
}
void
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 720c7725e..a313b4382 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -136,14 +136,14 @@ namespace MipsISA
const char *description() const;
/** Schedule This Event */
- void scheduleEvent(int delay);
+ void scheduleEvent(Cycles delay);
/** Unschedule This Event */
void unscheduleEvent();
};
// Schedule a CP0 Update Event
- void scheduleCP0Update(BaseCPU *cpu, int delay = 0);
+ void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
// If any changes have been made, then check the state for changes
// and if necessary alert the CPU
diff --git a/src/arch/mips/mmapped_ipr.hh b/src/arch/mips/mmapped_ipr.hh
index 14d6e3f42..4c84d05f2 100644
--- a/src/arch/mips/mmapped_ipr.hh
+++ b/src/arch/mips/mmapped_ipr.hh
@@ -45,13 +45,13 @@ class ThreadContext;
namespace MipsISA
{
-inline Tick
+inline Cycles
handleIprRead(ThreadContext *xc, Packet *pkt)
{
panic("No implementation for handleIprRead in MIPS\n");
}
-inline Tick
+inline Cycles
handleIprWrite(ThreadContext *xc, Packet *pkt)
{
panic("No implementation for handleIprWrite in MIPS\n");
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
index f163d3240..02e98a170 100755
--- a/src/arch/mips/mt.hh
+++ b/src/arch/mips/mt.hh
@@ -96,7 +96,7 @@ restoreThread(TC *tc)
// TODO: SET PC WITH AN EVENT INSTEAD OF INSTANTANEOUSLY
tc->pcState(restartPC);
- tc->activate(0);
+ tc->activate(Cycles(0));
warn("%i: Restoring thread %i in %s @ PC %x",
curTick(), tc->threadId(), tc->getCpuPtr()->name(), restartPC);
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 65432b4ea..f84819756 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -231,7 +231,7 @@ zeroRegisters(CPU *cpu)
void
startupCPU(ThreadContext *tc, int cpuId)
{
- tc->activate(0/*tc->threadId()*/);
+ tc->activate(Cycles(0));
}
void
diff --git a/src/arch/power/mmapped_ipr.hh b/src/arch/power/mmapped_ipr.hh
index a55ef8f7d..142253462 100644
--- a/src/arch/power/mmapped_ipr.hh
+++ b/src/arch/power/mmapped_ipr.hh
@@ -49,13 +49,13 @@ class ThreadContext;
namespace PowerISA
{
-inline Tick
+inline Cycles
handleIprRead(ThreadContext *xc, Packet *pkt)
{
panic("No implementation for handleIprRead in POWER\n");
}
-inline Tick
+inline Cycles
handleIprWrite(ThreadContext *xc, Packet *pkt)
{
panic("No implementation for handleIprWrite in POWER\n");
diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index c3868c189..8d9f97436 100644
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -59,7 +59,7 @@ void zeroRegisters(TC *tc);
inline void
startupCPU(ThreadContext *tc, int cpuId)
{
- tc->activate(0);
+ tc->activate(Cycles(0));
}
void
diff --git a/src/arch/sparc/mmapped_ipr.hh b/src/arch/sparc/mmapped_ipr.hh
index c13fdc910..153944e9d 100644
--- a/src/arch/sparc/mmapped_ipr.hh
+++ b/src/arch/sparc/mmapped_ipr.hh
@@ -44,13 +44,13 @@
namespace SparcISA
{
-inline Tick
+inline Cycles
handleIprRead(ThreadContext *xc, Packet *pkt)
{
return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
}
-inline Tick
+inline Cycles
handleIprWrite(ThreadContext *xc, Packet *pkt)
{
return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 37f1479b0..9faf297d6 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -848,7 +848,7 @@ TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
return NoFault;
}
-Tick
+Cycles
TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
{
Addr va = pkt->getAddr();
@@ -1030,10 +1030,10 @@ doMmuReadError:
(uint32_t)asi, va);
}
pkt->makeAtomicResponse();
- return tc->getCpuPtr()->ticks(1);
+ return Cycles(1);
}
-Tick
+Cycles
TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
{
uint64_t data = pkt->get<uint64_t>();
@@ -1283,7 +1283,7 @@ doMmuWriteError:
(uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
}
pkt->makeAtomicResponse();
- return tc->getCpuPtr()->ticks(1);
+ return Cycles(1);
}
void
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 89a049a8b..abbe2df3c 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -168,8 +168,8 @@ class TLB : public BaseTLB
* does not support the Checker model at the moment
*/
Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
- Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
- Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
+ Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt);
+ Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt);
void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
// Checkpointing
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 5948e0713..d3708d861 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -114,7 +114,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
if (!(tick_cmpr & ~mask(63)) && time > 0) {
if (tickCompare->scheduled())
cpu->deschedule(tickCompare);
- cpu->schedule(tickCompare, curTick() + time * cpu->ticks(1));
+ cpu->schedule(tickCompare, cpu->clockEdge(Cycles(time)));
}
panic("writing to TICK compare register %#X\n", val);
break;
@@ -130,7 +130,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
if (!(stick_cmpr & ~mask(63)) && time > 0) {
if (sTickCompare->scheduled())
cpu->deschedule(sTickCompare);
- cpu->schedule(sTickCompare, curTick() + time * cpu->ticks(1));
+ cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(time)));
}
DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
break;
@@ -200,7 +200,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
if (!(hstick_cmpr & ~mask(63)) && time > 0) {
if (hSTickCompare->scheduled())
cpu->deschedule(hSTickCompare);
- cpu->schedule(hSTickCompare, curTick() + time * cpu->ticks(1));
+ cpu->schedule(hSTickCompare, cpu->clockEdge(Cycles(time)));
}
DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
break;
@@ -329,19 +329,19 @@ ISA::processSTickCompare(ThreadContext *tc)
// since our microcode instructions take two cycles we need to check if
// we're actually at the correct cycle or we need to wait a little while
// more
- int ticks;
- ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
+ int delay;
+ delay = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
cpu->instCount();
- assert(ticks >= 0 && "stick compare missed interrupt cycle");
+ assert(delay >= 0 && "stick compare missed interrupt cycle");
- if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
+ if (delay == 0 || tc->status() == ThreadContext::Suspended) {
DPRINTF(Timer, "STick compare cycle reached at %#x\n",
(stick_cmpr & mask(63)));
if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
}
} else {
- cpu->schedule(sTickCompare, curTick() + ticks * cpu->ticks(1));
+ cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(delay)));
}
}
@@ -353,15 +353,15 @@ ISA::processHSTickCompare(ThreadContext *tc)
// since our microcode instructions take two cycles we need to check if
// we're actually at the correct cycle or we need to wait a little while
// more
- int ticks;
+ int delay;
if ( tc->status() == ThreadContext::Halted)
return;
- ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
+ delay = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
cpu->instCount();
- assert(ticks >= 0 && "hstick compare missed interrupt cycle");
+ assert(delay >= 0 && "hstick compare missed interrupt cycle");
- if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
+ if (delay == 0 || tc->status() == ThreadContext::Suspended) {
DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
(stick_cmpr & mask(63)));
if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
@@ -369,7 +369,7 @@ ISA::processHSTickCompare(ThreadContext *tc)
}
// Need to do something to cause interrupt to happen here !!! @todo
} else {
- cpu->schedule(hSTickCompare, curTick() + ticks * cpu->ticks(1));
+ cpu->schedule(hSTickCompare, cpu->clockEdge(Cycles(delay)));
}
}
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index b8e3b3f0e..285a40c26 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -77,7 +77,7 @@ startupCPU(ThreadContext *tc, int cpuId)
{
// Other CPUs will get activated by IPIs
if (cpuId == 0 || !FullSystem)
- tc->activate(0);
+ tc->activate(Cycles(0));
}
void copyRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/x86/mmapped_ipr.hh b/src/arch/x86/mmapped_ipr.hh
index f17b64cad..02c125171 100644
--- a/src/arch/x86/mmapped_ipr.hh
+++ b/src/arch/x86/mmapped_ipr.hh
@@ -53,7 +53,7 @@
namespace X86ISA
{
- inline Tick
+ inline Cycles
handleIprRead(ThreadContext *xc, Packet *pkt)
{
Addr offset = pkt->getAddr() & mask(3);
@@ -62,10 +62,10 @@ namespace X86ISA
// Make sure we don't trot off the end of data.
assert(offset + pkt->getSize() <= sizeof(MiscReg));
pkt->setData(((uint8_t *)&data) + offset);
- return 1;
+ return Cycles(1);
}
- inline Tick
+ inline Cycles
handleIprWrite(ThreadContext *xc, Packet *pkt)
{
Addr offset = pkt->getAddr() & mask(3);
@@ -76,7 +76,7 @@ namespace X86ISA
assert(offset + pkt->getSize() <= sizeof(MiscReg));
pkt->writeData(((uint8_t *)&data) + offset);
xc->setMiscReg(index, gtoh(data));
- return 1;
+ return Cycles(1);
}
}
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index acca97c49..65c1a9d32 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -176,7 +176,7 @@ void initCPU(ThreadContext *tc, int cpuId)
// @todo: Control the relative frequency, in this case 16:1, of
// the clocks in the Python code
- interrupts->setClock(tc->getCpuPtr()->ticks(16));
+ interrupts->setClock(tc->getCpuPtr()->clockPeriod() * 16);
// TODO Set the SMRAM base address (SMBASE) to 0x00030000
@@ -189,12 +189,12 @@ void initCPU(ThreadContext *tc, int cpuId)
void startupCPU(ThreadContext *tc, int cpuId)
{
if (cpuId == 0 || !FullSystem) {
- tc->activate(0);
+ tc->activate(Cycles(0));
} else {
// This is an application processor (AP). It should be initialized to
// look like only the BIOS POST has run on it and put then put it into
// a halted state.
- tc->suspend(0);
+ tc->suspend(Cycles(0));
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 00:58:29 +0000