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-rw-r--r--src/arch/arm/table_walker.cc33
-rw-r--r--src/arch/arm/table_walker.hh3
-rw-r--r--src/arch/x86/interrupts.cc5
-rw-r--r--src/arch/x86/interrupts.hh8
4 files changed, 24 insertions, 25 deletions
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index de3c38e78..8bffe68f8 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -45,13 +45,14 @@
#include "debug/Checkpoint.hh"
#include "debug/TLB.hh"
#include "debug/TLBVerbose.hh"
-#include "dev/io_device.hh"
#include "sim/system.hh"
using namespace ArmISA;
TableWalker::TableWalker(const Params *p)
- : MemObject(p), port(NULL), tlb(NULL), currState(NULL), pending(false),
+ : MemObject(p), port(this, params()->sys, params()->min_backoff,
+ params()->max_backoff, true),
+ tlb(NULL), currState(NULL), pending(false),
masterId(p->sys->getMasterId(name())),
doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this)
{
@@ -94,13 +95,7 @@ Port*
TableWalker::getPort(const std::string &if_name, int idx)
{
if (if_name == "port") {
- if (port != NULL)
- return port;
- System *sys = params()->sys;
- Tick minb = params()->min_backoff;
- Tick maxb = params()->max_backoff;
- port = new DmaPort(this, sys, minb, maxb, true);
- return port;
+ return &port;
}
return NULL;
}
@@ -225,24 +220,24 @@ TableWalker::processWalk()
}
if (currState->timing) {
- port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
- &doL1DescEvent, (uint8_t*)&currState->l1Desc.data,
- currState->tc->getCpuPtr()->ticks(1), flag);
+ port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
+ &doL1DescEvent, (uint8_t*)&currState->l1Desc.data,
+ currState->tc->getCpuPtr()->ticks(1), flag);
DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n",
stateQueueL1.size());
stateQueueL1.push_back(currState);
currState = NULL;
} else if (!currState->functional) {
- port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
- NULL, (uint8_t*)&currState->l1Desc.data,
- currState->tc->getCpuPtr()->ticks(1), flag);
+ port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
+ NULL, (uint8_t*)&currState->l1Desc.data,
+ currState->tc->getCpuPtr()->ticks(1), flag);
doL1Descriptor();
f = currState->fault;
} else {
RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag, masterId);
PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
pkt->dataStatic((uint8_t*)&currState->l1Desc.data);
- port->sendFunctional(pkt);
+ port.sendFunctional(pkt);
doL1Descriptor();
delete req;
delete pkt;
@@ -574,11 +569,11 @@ TableWalker::doL1Descriptor()
if (currState->timing) {
currState->delayed = true;
- port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
+ port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
&doL2DescEvent, (uint8_t*)&currState->l2Desc.data,
currState->tc->getCpuPtr()->ticks(1));
} else if (!currState->functional) {
- port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
+ port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
NULL, (uint8_t*)&currState->l2Desc.data,
currState->tc->getCpuPtr()->ticks(1));
doL2Descriptor();
@@ -586,7 +581,7 @@ TableWalker::doL1Descriptor()
RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0, masterId);
PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
pkt->dataStatic((uint8_t*)&currState->l2Desc.data);
- port->sendFunctional(pkt);
+ port.sendFunctional(pkt);
doL2Descriptor();
delete req;
delete pkt;
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 520bfd9ac..22d2da5b3 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -44,6 +44,7 @@
#include "arch/arm/miscregs.hh"
#include "arch/arm/tlb.hh"
+#include "dev/io_device.hh"
#include "mem/mem_object.hh"
#include "mem/request.hh"
#include "params/ArmTableWalker.hh"
@@ -328,7 +329,7 @@ class TableWalker : public MemObject
/** Port to issue translation requests from */
- DmaPort *port;
+ DmaPort port;
/** TLB that is initiating these table walks */
TLB *tlb;
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index 612244f49..6a9f07af2 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -554,7 +554,7 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
break;
}
pendingIPIs += apics.size();
- intPort->sendMessage(apics, message, timing);
+ intPort.sendMessage(apics, message, timing);
newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
}
break;
@@ -612,7 +612,8 @@ X86ISA::Interrupts::Interrupts(Params * p) :
pendingInit(false), initVector(0),
pendingStartup(false), startupVector(0),
startedUp(false), pendingUnmaskableInt(false),
- pendingIPIs(0), cpu(NULL)
+ pendingIPIs(0), cpu(NULL),
+ intSlavePort(name() + ".int_slave", this, this, latency)
{
pioSize = PageBytes;
memset(regs, 0, sizeof(regs));
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 13ad2069b..abf3040bd 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -188,6 +188,9 @@ class Interrupts : public BasicPioDevice, IntDev
int initialApicId;
+ // Port for receiving interrupts
+ IntPort intSlavePort;
+
public:
int getInitialApicId() { return initialApicId; }
@@ -242,10 +245,9 @@ class Interrupts : public BasicPioDevice, IntDev
// Python class we also need two ports even if they are
// identical
if (if_name == "int_master") {
- return intPort;
+ return &intPort;
} else if (if_name == "int_slave") {
- // memory leak...but will be removed in the next patch
- return new IntPort(name() + ".int_slave", this, this, latency);
+ return &intSlavePort;
}
return BasicPioDevice::getPort(if_name, idx);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 06:06:30 +0000