diff options
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/SConscript | 3 | ||||
| -rw-r--r-- | src/arch/alpha/ev5.cc | 4 | ||||
| -rw-r--r-- | src/arch/alpha/isa/decoder.isa | 2 | ||||
| -rw-r--r-- | src/arch/sparc/regfile.hh | 3 |
4 files changed, 5 insertions, 7 deletions
diff --git a/src/arch/SConscript b/src/arch/SConscript index dd616174c..c90694a68 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -146,7 +146,6 @@ env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder }) isa = env['TARGET_ISA'] # someday this may be a list of ISAs # Let the target architecture define what additional sources it needs -sources += SConscript(os.path.join(isa, 'SConscript'), - exports = 'env', duplicate = False) +sources += SConscript(os.path.join(isa, 'SConscript'), exports = 'env') Return('sources') diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index c419762b7..7d6894733 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -41,7 +41,7 @@ #include "cpu/thread_context.hh" #include "kern/kernel_stats.hh" #include "sim/debug.hh" -#include "sim/sim_events.hh" +#include "sim/sim_exit.hh" #if FULL_SYSTEM @@ -571,7 +571,7 @@ SimpleThread::simPalCheck(int palFunc) case PAL::halt: halt(); if (--System::numSystemsRunning == 0) - new SimExitEvent("all cpus halted"); + exitSimLoop("all cpus halted"); break; case PAL::bpt: diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index fab2ca2e1..fbdb119b6 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -697,7 +697,7 @@ decode OPCODE default Unknown::unknown() { 0x00: decode PALFUNC { format EmulatedCallPal { 0x00: halt ({{ - SimExit(curTick, "halt instruction encountered"); + exitSimLoop(curTick, "halt instruction encountered"); }}, IsNonSpeculative); 0x83: callsys({{ xc->syscall(R0); diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index aaf1fcf24..760edc41e 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -61,8 +61,7 @@ namespace SparcISA const int HprStart = 64; const int MiscStart = 96; - - const uint64_t Bit64 = 0x8000000000000000; + const uint64_t Bit64 = (1ULL << 63); class IntRegFile { |