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-rw-r--r--src/arch/alpha/isa.cc5
-rw-r--r--src/arch/alpha/isa.hh7
-rw-r--r--src/arch/arm/isa.cc4
-rw-r--r--src/arch/arm/isa.hh4
-rw-r--r--src/arch/mips/isa.cc9
-rw-r--r--src/arch/mips/isa.hh11
-rw-r--r--src/arch/power/isa.hh4
-rw-r--r--src/arch/riscv/isa.cc6
-rw-r--r--src/arch/riscv/isa.hh4
-rw-r--r--src/arch/sparc/isa.hh7
-rw-r--r--src/arch/sparc/ua2005.cc2
11 files changed, 29 insertions, 34 deletions
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
index 32d1aff65..685ddd479 100644
--- a/src/arch/alpha/isa.cc
+++ b/src/arch/alpha/isa.cc
@@ -114,7 +114,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
}
void
-ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
+ISA::setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -140,8 +140,7 @@ ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
}
void
-ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
- ThreadID tid)
+ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, ThreadID tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index 36e708450..54e12022a 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -77,10 +77,9 @@ namespace AlphaISA
MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
- ThreadID tid = 0);
- void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
- ThreadID tid = 0);
+ void setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid=0);
+ void setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc,
+ ThreadID tid=0);
void
clear()
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index ba7c09509..6cbf8db90 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -710,7 +710,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
}
void
-ISA::setMiscRegNoEffect(int misc_reg, const RegVal &val)
+ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
{
assert(misc_reg < NumMiscRegs);
@@ -732,7 +732,7 @@ ISA::setMiscRegNoEffect(int misc_reg, const RegVal &val)
}
void
-ISA::setMiscReg(int misc_reg, const RegVal &val, ThreadContext *tc)
+ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
{
RegVal newVal = val;
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index c365a1bd0..60c572833 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -430,8 +430,8 @@ namespace ArmISA
public:
RegVal readMiscRegNoEffect(int misc_reg) const;
RegVal readMiscReg(int misc_reg, ThreadContext *tc);
- void setMiscRegNoEffect(int misc_reg, const RegVal &val);
- void setMiscReg(int misc_reg, const RegVal &val, ThreadContext *tc);
+ void setMiscRegNoEffect(int misc_reg, RegVal val);
+ void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc);
RegId
flattenRegId(const RegId& regId) const
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index df70bacbb..6f109f76f 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -445,7 +445,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
}
void
-ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
+ISA::setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid)
{
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
@@ -458,7 +458,7 @@ ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
}
void
-ISA::setRegMask(int misc_reg, const MiscReg &val, ThreadID tid)
+ISA::setRegMask(int misc_reg, MiscReg val, ThreadID tid)
{
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
@@ -473,8 +473,7 @@ ISA::setRegMask(int misc_reg, const MiscReg &val, ThreadID tid)
// be overwritten. Make sure to handle those particular registers
// with care!
void
-ISA::setMiscReg(int misc_reg, const MiscReg &val,
- ThreadContext *tc, ThreadID tid)
+ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, ThreadID tid)
{
int reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
@@ -497,7 +496,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val,
* (setRegWithEffect)
*/
MiscReg
-ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
+ISA::filterCP0Write(int misc_reg, int reg_sel, MiscReg val)
{
MiscReg retVal = val;
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 885ca2ff7..ffcb3f1dc 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -94,14 +94,13 @@ namespace MipsISA
MiscReg readMiscReg(int misc_reg,
ThreadContext *tc, ThreadID tid = 0);
- MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val);
- void setRegMask(int misc_reg, const MiscReg &val, ThreadID tid = 0);
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
- ThreadID tid = 0);
+ MiscReg filterCP0Write(int misc_reg, int reg_sel, MiscReg val);
+ void setRegMask(int misc_reg, MiscReg val, ThreadID tid = 0);
+ void setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid=0);
//template <class TC>
- void setMiscReg(int misc_reg, const MiscReg &val,
- ThreadContext *tc, ThreadID tid = 0);
+ void setMiscReg(int misc_reg, MiscReg val,
+ ThreadContext *tc, ThreadID tid=0);
//////////////////////////////////////////////////////////
//
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 9769f8fd1..4e9fdb00a 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -76,13 +76,13 @@ class ISA : public SimObject
}
void
- setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+ setMiscRegNoEffect(int misc_reg, MiscReg val)
{
fatal("Power does not currently have any misc regs defined\n");
}
void
- setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
+ setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc)
{
fatal("Power does not currently have any misc regs defined\n");
}
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index d99a74220..0f184b882 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -164,7 +164,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
}
void
-ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+ISA::setMiscRegNoEffect(int misc_reg, MiscReg val)
{
if (misc_reg > NumMiscRegs || misc_reg < 0) {
// Illegal CSR
@@ -175,7 +175,7 @@ ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
}
void
-ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
+ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc)
{
if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) {
// Ignore writes to HPM counters for now
@@ -200,4 +200,4 @@ RiscvISA::ISA *
RiscvISAParams::create()
{
return new RiscvISA::ISA(this);
-} \ No newline at end of file
+}
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index f96b07275..2602f6dde 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -76,8 +76,8 @@ class ISA : public SimObject
MiscReg readMiscRegNoEffect(int misc_reg) const;
MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
- void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
+ void setMiscRegNoEffect(int misc_reg, MiscReg val);
+ void setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc);
RegId flattenRegId(const RegId &regId) const { return regId; }
int flattenIntIndex(int reg) const { return reg; }
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 82fee0d00..9209ba3de 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -116,7 +116,7 @@ class ISA : public SimObject
// These need to check the int_dis field and if 0 then
// set appropriate bit in softint and checkinterrutps on the cpu
- void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
+ void setFSReg(int miscReg, MiscReg val, ThreadContext *tc);
MiscReg readFSReg(int miscReg, ThreadContext * tc);
// Update interrupt state on softint or pil change
@@ -186,9 +186,8 @@ class ISA : public SimObject
MiscReg readMiscRegNoEffect(int miscReg) const;
MiscReg readMiscReg(int miscReg, ThreadContext *tc);
- void setMiscRegNoEffect(int miscReg, const MiscReg val);
- void setMiscReg(int miscReg, const MiscReg val,
- ThreadContext *tc);
+ void setMiscRegNoEffect(int miscReg, MiscReg val);
+ void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
RegId
flattenRegId(const RegId& regId) const
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index d8af29b91..1a248d342 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -88,7 +88,7 @@ getMiscRegName(RegIndex index)
}
void
-ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
+ISA::setFSReg(int miscReg, MiscReg val, ThreadContext *tc)
{
BaseCPU *cpu = tc->getCpuPtr();
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-01 19:21:54 +0000