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-rw-r--r--src/arch/arm/isa.hh12
-rw-r--r--src/arch/arm/linux/system.cc5
-rw-r--r--src/arch/arm/linux/system.hh4
-rw-r--r--src/arch/arm/pagetable.hh87
-rw-r--r--src/arch/arm/table_walker.cc16
-rw-r--r--src/arch/arm/table_walker.hh2
-rw-r--r--src/arch/arm/tlb.cc14
-rw-r--r--src/arch/arm/tlb.hh2
8 files changed, 87 insertions, 55 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 8318417f5..88d08e971 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -178,10 +178,18 @@ namespace ArmISA
}
void serialize(EventManager *em, std::ostream &os)
- {}
+ {
+ DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
+ SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
+ }
void unserialize(EventManager *em, Checkpoint *cp,
const std::string &section)
- {}
+ {
+ DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
+ UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
+ CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
+ updateRegMap(tmp_cpsr);
+ }
ISA()
{
diff --git a/src/arch/arm/linux/system.cc b/src/arch/arm/linux/system.cc
index ddf7f19f3..38024c058 100644
--- a/src/arch/arm/linux/system.cc
+++ b/src/arch/arm/linux/system.cc
@@ -99,9 +99,9 @@ LinuxArmSystem::LinuxArmSystem(Params *p)
}
void
-LinuxArmSystem::startup()
+LinuxArmSystem::initState()
{
- ArmSystem::startup();
+ ArmSystem::initState();
ThreadContext *tc = threadContexts[0];
// Set the initial PC to be at start of the kernel code
@@ -117,7 +117,6 @@ LinuxArmSystem::~LinuxArmSystem()
{
}
-
LinuxArmSystem *
LinuxArmSystemParams::create()
{
diff --git a/src/arch/arm/linux/system.hh b/src/arch/arm/linux/system.hh
index 12c86db25..4e5ebcd73 100644
--- a/src/arch/arm/linux/system.hh
+++ b/src/arch/arm/linux/system.hh
@@ -67,8 +67,8 @@ class LinuxArmSystem : public ArmSystem
LinuxArmSystem(Params *p);
~LinuxArmSystem();
- /** Initialize the CPU for booting */
- void startup();
+ void initState();
+
private:
#ifndef NDEBUG
/** Event to halt the simulator if the kernel calls panic() */
diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh
index 76b0e3bb8..46322046f 100644
--- a/src/arch/arm/pagetable.hh
+++ b/src/arch/arm/pagetable.hh
@@ -48,6 +48,8 @@
#include "arch/arm/vtophys.hh"
#include "config/full_system.hh"
+#include "sim/serialize.hh"
+
namespace ArmISA {
struct VAddr
@@ -71,39 +73,6 @@ struct PTE
};
-struct TlbRange
-{
- Addr va;
- Addr size;
- int contextId;
- bool global;
-
- inline bool
- operator<(const TlbRange &r2) const
- {
- if (!(global || r2.global)) {
- if (contextId < r2.contextId)
- return true;
- else if (contextId > r2.contextId)
- return false;
- }
-
- if (va < r2.va)
- return true;
- return false;
- }
-
- inline bool
- operator==(const TlbRange &r2) const
- {
- return va == r2.va &&
- size == r2.size &&
- contextId == r2.contextId &&
- global == r2.global;
- }
-};
-
-
// ITB/DTB table entry
struct TlbEntry
{
@@ -143,10 +112,8 @@ struct TlbEntry
// Access permissions
bool xn; // Execute Never
- uint8_t ap:3; // Access permissions bits
- uint8_t domain:4; // Access Domain
-
- TlbRange range; // For fast TLB searching
+ uint8_t ap; // Access permissions bits
+ uint8_t domain; // Access Domain
//Construct an entry that maps to physical address addr for SE mode
TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr)
@@ -196,9 +163,49 @@ struct TlbEntry
return (pfn << N) | (va & size);
}
- void serialize(std::ostream &os) { panic("Need to Implement\n"); }
- void unserialize(Checkpoint *cp, const std::string &section)
- { panic("Need to Implement\n");}
+ void
+ serialize(std::ostream &os)
+ {
+ SERIALIZE_SCALAR(pfn);
+ SERIALIZE_SCALAR(size);
+ SERIALIZE_SCALAR(vpn);
+ SERIALIZE_SCALAR(asid);
+ SERIALIZE_SCALAR(N);
+ SERIALIZE_SCALAR(global);
+ SERIALIZE_SCALAR(valid);
+ SERIALIZE_SCALAR(nonCacheable);
+ SERIALIZE_SCALAR(sNp);
+ SERIALIZE_ENUM(mtype);
+ SERIALIZE_SCALAR(innerAttrs);
+ SERIALIZE_SCALAR(outerAttrs);
+ SERIALIZE_SCALAR(shareable);
+ SERIALIZE_SCALAR(attributes);
+ SERIALIZE_SCALAR(xn);
+ SERIALIZE_SCALAR(ap);
+ SERIALIZE_SCALAR(domain);
+ }
+ void
+ unserialize(Checkpoint *cp, const std::string &section)
+ {
+ UNSERIALIZE_SCALAR(pfn);
+ UNSERIALIZE_SCALAR(size);
+ UNSERIALIZE_SCALAR(vpn);
+ UNSERIALIZE_SCALAR(asid);
+ UNSERIALIZE_SCALAR(N);
+ UNSERIALIZE_SCALAR(global);
+ UNSERIALIZE_SCALAR(valid);
+ UNSERIALIZE_SCALAR(nonCacheable);
+ UNSERIALIZE_SCALAR(sNp);
+ UNSERIALIZE_ENUM(mtype);
+ UNSERIALIZE_SCALAR(innerAttrs);
+ UNSERIALIZE_SCALAR(outerAttrs);
+ UNSERIALIZE_SCALAR(shareable);
+ UNSERIALIZE_SCALAR(attributes);
+ UNSERIALIZE_SCALAR(xn);
+ UNSERIALIZE_SCALAR(ap);
+ UNSERIALIZE_SCALAR(domain);
+ }
+
};
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index ddf9fe5d3..c7c00924d 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -59,10 +59,20 @@ TableWalker::~TableWalker()
}
-unsigned int
-drain(Event *de)
+unsigned int TableWalker::drain(Event *de)
{
- panic("Not implemented\n");
+ if (stateQueueL1.size() != 0 || stateQueueL2.size() != 0)
+ {
+ changeState(Draining);
+ DPRINTF(Checkpoint, "TableWalker busy, wait to drain\n");
+ return 1;
+ }
+ else
+ {
+ changeState(Drained);
+ DPRINTF(Checkpoint, "TableWalker free, no need to drain\n");
+ return 0;
+ }
}
Port*
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index fde553ff4..0804997c3 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -350,7 +350,7 @@ class TableWalker : public MemObject
return dynamic_cast<const Params *>(_params);
}
- virtual unsigned int drain(Event *de) { panic("write me\n"); }
+ virtual unsigned int drain(Event *de);
virtual Port *getPort(const std::string &if_name, int idx = -1);
Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 239d5d8a2..4f1279404 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -245,14 +245,24 @@ TLB::flushMva(Addr mva)
void
TLB::serialize(ostream &os)
{
- panic("Implement Serialize\n");
+ DPRINTF(Checkpoint, "Serializing Arm TLB\n");
+
+ SERIALIZE_SCALAR(_attr);
+ for(int i = 0; i < size; i++){
+ nameOut(os, csprintf("%s.TlbEntry%d", name(), i));
+ table[i].serialize(os);
+ }
}
void
TLB::unserialize(Checkpoint *cp, const string &section)
{
+ DPRINTF(Checkpoint, "Unserializing Arm TLB\n");
- panic("Need to properly unserialize TLB\n");
+ UNSERIALIZE_SCALAR(_attr);
+ for(int i = 0; i < size; i++){
+ table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i));
+ }
}
void
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 2d3661f7d..bd723e8d1 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -83,8 +83,6 @@ class TLB : public BaseTLB
MustBeOne = 0x80
};
protected:
- typedef std::multimap<Addr, int> PageTable;
- PageTable lookupTable; // Quick lookup into page table
TlbEntry *table; // the Page Table
int size; // TLB Size
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 18:11:21 +0000