9 files changed, 185 insertions, 96 deletions
diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index 7998cbdf1..ba577e8cb 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -135,6 +135,13 @@ handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
     return true;
 }
 
+template <class XC>
+inline void
+globalClearExclusive(XC *xc)
+{
+    xc->getCpuPtr()->wakeup(xc->threadId());
+}
+
 } // namespace AlphaISA
 
 #endif // __ARCH_ALPHA_LOCKED_MEM_HH__
diff --git a/src/arch/arm/locked_mem.hh b/src/arch/arm/locked_mem.hh
index 8aa181245..2fcbc4a92 100644
--- a/src/arch/arm/locked_mem.hh
+++ b/src/arch/arm/locked_mem.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013 ARM Limited
+ * Copyright (c) 2012-2013,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -148,6 +148,20 @@ handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
     return true;
 }
 
+template <class XC>
+inline void
+globalClearExclusive(XC *xc)
+{
+    // A spinlock would typically include a Wait For Event (WFE) to
+    // conserve energy. The ARMv8 architecture specifies that an event
+    // is automatically generated when clearing the exclusive monitor
+    // to wake up the processor in WFE.
+    DPRINTF(LLSC,"Clearing lock and signaling sev\n");
+    xc->setMiscReg(MISCREG_LOCKFLAG, false);
+    // Implement ARMv8 WFE/SEV semantics
+    xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
+    xc->getCpuPtr()->wakeup(xc->threadId());
+}
 
 } // namespace ArmISA
 
diff --git a/src/arch/generic/locked_mem.hh b/src/arch/generic/locked_mem.hh
new file mode 100644
index 000000000..68a4ff540
--- /dev/null
+++ b/src/arch/generic/locked_mem.hh
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ */
+
+#ifndef __ARCH_GENERIC_LOCKED_MEM_HH__
+#define __ARCH_GENERIC_LOCKED_MEM_HH__
+
+/**
+ * @file
+ *
+ * Generic helper functions for locked memory accesses.
+ */
+
+#include "config/the_isa.hh"
+#include "mem/packet.hh"
+#include "mem/request.hh"
+
+namespace TheISA
+{
+template <class XC>
+inline void
+handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
+{
+}
+
+template <class XC>
+inline void
+handleLockedRead(XC *xc, Request *req)
+{
+}
+
+template <class XC>
+inline void
+handleLockedSnoopHit(XC *xc)
+{
+}
+
+
+template <class XC>
+inline bool
+handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
+{
+    return true;
+}
+
+template <class XC>
+inline void
+globalClearExclusive(XC *xc)
+{
+}
+
+} // namespace Generic ISA
+
+#endif
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index a1d89de99..61c689955 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -139,6 +139,13 @@ handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
     return true;
 }
 
+template <class XC>
+inline void
+globalClearExclusive(XC *xc)
+{
+    xc->getCpuPtr()->wakeup(xc->threadId());
+}
+
 } // namespace MipsISA
 
 #endif
diff --git a/src/arch/null/locked_mem.hh b/src/arch/null/locked_mem.hh
new file mode 100644
index 000000000..f5ecaf7dc
--- /dev/null
+++ b/src/arch/null/locked_mem.hh
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ */
+
+#ifndef __ARCH_NULL_LOCKED_MEM_HH__
+#define __ARCH_NULL_LOCKED_MEM_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for locked memory accesses.
+ */
+
+#include "arch/generic/locked_mem.hh"
+
+#endif
diff --git a/src/arch/power/locked_mem.hh b/src/arch/power/locked_mem.hh
index d962f9aff..d7abc64f0 100644
--- a/src/arch/power/locked_mem.hh
+++ b/src/arch/power/locked_mem.hh
@@ -41,37 +41,6 @@
  * ISA-specific helper functions for locked memory accesses.
  */
 
-#include "mem/packet.hh"
-#include "mem/request.hh"
-
-namespace PowerISA
-{
-
-template <class XC>
-inline void
-handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
-{
-}
-
-template <class XC>
-inline void
-handleLockedRead(XC *xc, Request *req)
-{
-}
-
-template <class XC>
-inline void
-handleLockedSnoopHit(XC *xc)
-{
-}
-
-template <class XC>
-inline bool
-handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
-{
-    return true;
-}
-
-} // namespace PowerISA
+#include "arch/generic/locked_mem.hh"
 
 #endif // __ARCH_POWER_LOCKED_MEM_HH__
diff --git a/src/arch/riscv/locked_mem.hh b/src/arch/riscv/locked_mem.hh
index d7fc0ca5a..f334385b1 100644
--- a/src/arch/riscv/locked_mem.hh
+++ b/src/arch/riscv/locked_mem.hh
@@ -126,6 +126,13 @@ handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
     return true;
 }
 
+template <class XC>
+inline void
+globalClearExclusive(XC *xc)
+{
+    xc->getCpuPtr()->wakeup(xc->threadId());
+}
+
 } // namespace RiscvISA
 
 #endif // __ARCH_RISCV_LOCKED_MEM_HH__
diff --git a/src/arch/sparc/locked_mem.hh b/src/arch/sparc/locked_mem.hh
index b28179481..90760d586 100644
--- a/src/arch/sparc/locked_mem.hh
+++ b/src/arch/sparc/locked_mem.hh
@@ -37,38 +37,6 @@
  * ISA-specific helper functions for locked memory accesses.
  */
 
-#include "mem/packet.hh"
-#include "mem/request.hh"
-
-namespace SparcISA
-{
-template <class XC>
-inline void
-handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
-{
-}
-
-template <class XC>
-inline void
-handleLockedRead(XC *xc, Request *req)
-{
-}
-
-template <class XC>
-inline void
-handleLockedSnoopHit(XC *xc)
-{
-}
-
-
-template <class XC>
-inline bool
-handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
-{
-    return true;
-}
-
-
-} // namespace SparcISA
+#include "arch/generic/locked_mem.hh"
 
 #endif
diff --git a/src/arch/x86/locked_mem.hh b/src/arch/x86/locked_mem.hh
index 51cfb2ea3..0a746eb4e 100644
--- a/src/arch/x86/locked_mem.hh
+++ b/src/arch/x86/locked_mem.hh
@@ -37,35 +37,6 @@
  * ISA-specific helper functions for locked memory accesses.
  */
 
-#include "mem/packet.hh"
-#include "mem/request.hh"
-
-namespace X86ISA
-{
-    template <class XC>
-    inline void
-    handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
-    {
-    }
-
-    template <class XC>
-    inline void
-    handleLockedRead(XC *xc, Request *req)
-    {
-    }
-
-    template <class XC>
-    inline bool
-    handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
-    {
-        return true;
-    }
-
-    template <class XC>
-    inline void
-    handleLockedSnoopHit(XC *xc)
-    {
-    }
-}
+#include "arch/generic/locked_mem.hh"
 
 #endif // __ARCH_X86_LOCKEDMEM_HH__