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-rw-r--r--src/arch/alpha/ev5.cc2
-rw-r--r--src/arch/sparc/regfile.hh3
2 files changed, 2 insertions, 3 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index dddefeb28..7d6894733 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -41,7 +41,7 @@
#include "cpu/thread_context.hh"
#include "kern/kernel_stats.hh"
#include "sim/debug.hh"
-#include "sim/sim_events.hh"
+#include "sim/sim_exit.hh"
#if FULL_SYSTEM
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index aaf1fcf24..760edc41e 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -61,8 +61,7 @@ namespace SparcISA
const int HprStart = 64;
const int MiscStart = 96;
-
- const uint64_t Bit64 = 0x8000000000000000;
+ const uint64_t Bit64 = (1ULL << 63);
class IntRegFile
{