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-rw-r--r--src/arch/riscv/isa.cc2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 4e36d5596..cc86752ab 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -112,6 +112,8 @@ RegVal
ISA::readMiscReg(int misc_reg, ThreadContext *tc)
{
switch (misc_reg) {
+ case MISCREG_HARTID:
+ return tc->contextId();
case MISCREG_CYCLE:
if (hpmCounterEnabled(MISCREG_CYCLE)) {
DPRINTF(RiscvMisc, "Cycle counter at: %llu.\n",