diff options
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/isa.cc | 3 | ||||
| -rw-r--r-- | src/arch/arm/table_walker.cc | 1 | ||||
| -rw-r--r-- | src/arch/x86/isa.cc | 4 | ||||
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 3 |
4 files changed, 8 insertions, 3 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index a490e5fb7..44e4ff376 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1653,6 +1653,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); } } + M5_FALLTHROUGH; case MISCREG_TTBR0: case MISCREG_TTBR1: { @@ -1666,12 +1667,14 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) } } } + M5_FALLTHROUGH; case MISCREG_SCTLR_EL1: { tc->getITBPtr()->invalidateMiscReg(); tc->getDTBPtr()->invalidateMiscReg(); setMiscRegNoEffect(misc_reg, newVal); } + M5_FALLTHROUGH; case MISCREG_CONTEXTIDR: case MISCREG_PRRR: case MISCREG_NMRR: diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 2d6664264..63b67f56a 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -1398,6 +1398,7 @@ TableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te, case 0x1 ... 0x3: // Normal Memory, Inner Write-through transient case 0x9 ... 0xb: // Normal Memory, Inner Write-through non-transient warn_if(!attr_hi, "Unpredictable behavior"); + M5_FALLTHROUGH; case 0x4: // Device-nGnRE memory or // Normal memory, Inner Non-cacheable case 0x8: // Device-nGRE memory or diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc index 9dd7fbb52..f092f4418 100644 --- a/src/arch/x86/isa.cc +++ b/src/arch/x86/isa.cc @@ -316,7 +316,7 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) break; case MISCREG_DR4: miscReg = MISCREG_DR6; - /* Fall through to have the same effects as DR6. */ + M5_FALLTHROUGH; case MISCREG_DR6: { DR6 dr6 = regVal[MISCREG_DR6]; @@ -333,7 +333,7 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) break; case MISCREG_DR5: miscReg = MISCREG_DR7; - /* Fall through to have the same effects as DR7. */ + M5_FALLTHROUGH; case MISCREG_DR7: { DR7 dr7 = regVal[MISCREG_DR7]; diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 4fd3b2aa6..2d5ae048a 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -1427,6 +1427,7 @@ let {{ if (bits(newVal, 63, 4)) fault = std::make_shared<GeneralProtection>(0); } + break; default: fault = std::make_shared<GenericISA::M5PanicFault>( "Unrecognized control register %d.\\n", dest); @@ -1528,7 +1529,7 @@ let {{ fault = std::make_shared<GeneralProtection>(selector); break; } - // Fall through on purpose + M5_FALLTHROUGH; case SegIntGateCheck: // Make sure the gate's the right type. if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || |