diff options
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/ArmTLB.py | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py index 4a6b3e7cd..d2334630e 100644 --- a/src/arch/arm/ArmTLB.py +++ b/src/arch/arm/ArmTLB.py @@ -90,11 +90,17 @@ class ArmStage2MMU(SimObject): class ArmStage2IMMU(ArmStage2MMU): # We rely on the itb being a parameter of the CPU, and get the # appropriate object that way - tlb = Parent.itb + tlb = Parent.any stage2_tlb = ArmStage2TLB() class ArmStage2DMMU(ArmStage2MMU): # We rely on the dtb being a parameter of the CPU, and get the # appropriate object that way - tlb = Parent.dtb + tlb = Parent.any stage2_tlb = ArmStage2TLB() + +class ArmITB(ArmTLB): + stage2_mmu = ArmStage2IMMU() + +class ArmDTB(ArmTLB): + stage2_mmu = ArmStage2DMMU() |