8 files changed, 0 insertions, 20 deletions
diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index e2e8fedcc..d87d24575 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -46,9 +46,6 @@ using AlphaISAInst::MaxInstDestRegs;
 // Locked read/write flags are can't be detected by the ISA parser
 const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
 
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
 // Not applicable to Alpha
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 8960f9f92..fd59f3ed8 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -77,9 +77,6 @@ using VecPredRegContainer = ::DummyVecPredRegContainer;
 constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
 constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
 
-// condition code register; must be at least 32 bits for FpCondCodes
-typedef uint64_t CCReg;
-
 // Constants Related to the number of registers
 const int NumIntArchRegs = NUM_ARCH_INTREGS;
 // The number of single precision floating point registers
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index 702e48623..27536baea 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -283,9 +283,6 @@ const int NumMiscRegs = MISCREG_NUMREGS;
 
 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
 
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
 // Not applicable to MIPS
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;
diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index 49ea4c79c..0ad0ea4bd 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -47,7 +47,6 @@
 
 namespace NullISA {
 
-typedef uint8_t CCReg;
 const RegIndex ZeroReg = 0;
 
 // Not applicable to null
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 9d793d390..a494425cd 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -46,9 +46,6 @@ using PowerISAInst::MaxInstDestRegs;
 // be detected by it. Manually add it here.
 const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
 
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
 // Not applicable to Power
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index e2d1d154b..c2e1fd2b5 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -64,8 +64,6 @@ using RiscvISAInst::MaxInstSrcRegs;
 using RiscvISAInst::MaxInstDestRegs;
 const int MaxMiscDestRegs = 1;
 
-typedef uint8_t CCReg; // Not applicable to Riscv
-
 // Not applicable to RISC-V
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index d9b182e7f..0c11f66b2 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -46,9 +46,6 @@ using SparcISAInst::MaxInstSrcRegs;
 using SparcISAInst::MaxInstDestRegs;
 using SparcISAInst::MaxMiscDestRegs;
 
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
 // Not applicable to SPARC
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index ea75ec907..0590abe49 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -96,8 +96,6 @@ const int FramePointerReg = INTREG_RBP;
 // value
 const int SyscallPseudoReturnReg = INTREG_RDX;
 
-typedef uint64_t CCReg;
-
 // Not applicable to x86
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;